hard_fault_handler.cpp.in

// coding: utf-8
// ----------------------------------------------------------------------------
/* Copyright (c) 2011, Roboterclub Aachen e.V.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Roboterclub Aachen e.V. nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY ROBOTERCLUB AACHEN E.V. ''AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ROBOTERCLUB AACHEN E.V. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
// ----------------------------------------------------------------------------

#include <stdint.h>

#include "../../../device.hpp"

%% if parameters.enable_hardfault_handler_led or (parameters.enable_hardfault_handler_log != "false")
#include "../../clock/generic/common_clock.hpp"
%% endif

%% if parameters.enable_hardfault_handler_led
	%% if target is stm32f1
#include "../../gpio/stm32f1/gpio.hpp"
	%% else
#include "../../gpio/stm32/gpio.hpp"
	%% endif

extern "C" void _initHardFaultHandlerLed() __attribute__((optimize("Os")));
extern "C" void _initHardFaultHandlerLed()
{
	xpcc::stm32::Gpio{{ parameters.hardfault_handler_led_port }}{{ parameters.hardfault_handler_led_pin }}::setOutput();
}

extern "C" void _toggleHardFaultHandlerLed() __attribute__((optimize("Os")));
extern "C" void _toggleHardFaultHandlerLed()
{
	xpcc::stm32::Gpio{{ parameters.hardfault_handler_led_port }}{{ parameters.hardfault_handler_led_pin }}::toggle();
}

%% endif

%% if parameters.enable_hardfault_handler_log != "false"
#include <xpcc/debug/logger.hpp>
	%% set id = parameters.hardfault_handler_uart

	%% if id in [1, 2, 3, 6]
		%%	set uart = "Usart"
	%% elif id in [4, 5, 7, 8]
		%%	set uart = "Uart"
	%% endif

#include "../../uart/stm32/uart_{{ id }}.hpp"

XPCC_ISR_DECL({{ uart | upper ~ id }});

// since the hard fault handler cannot be preempted by any other handler or IRQ
// we have to manually call it here. Not pretty, but it works.
extern "C"
void flushUart()
{
	while(not xpcc::stm32::{{ uart ~ id }}::isWriteFinished())
	{
		if (xpcc::stm32::{{ uart }}Hal{{ id }}::isTransmitRegisterEmpty())
		{
			XPCC_ISR_CALL({{ uart | upper ~ id }});
		}
	}
}

const char *valid   = "";
const char *invalid = " [INVALID]";

extern const uint32_t __stack_start;
extern const uint32_t __stack_end;
extern const uint32_t __main_stack_top;
extern const uint32_t __process_stack_top;

constexpr uint16_t usage_fault_mask = 0x30f;
constexpr uint8_t    bus_fault_mask = 0xbf;
constexpr uint8_t    mem_fault_mask = 0xbb;
%% endif

%% if parameters.enable_hardfault_handler_log == "true" and target is not cortex_m0
const char *mem_fault_bits[] = {
	"MMARVALID",
	"MLSPERR",
	"MSTKERR",
	"MUNSTKERR",
	"DACCVIOL",
	"IACCVIOL"
};
const char *bus_fault_bits[] = {
	"BFARVALID",
	"LSPERR",
	"STKERR",
	"UNSTKERR",
	"IMPRECISERR",
	"PRECISERR",
	"IBUSERR"
};
const char *usage_fault_bits[] = {
	"DIVBYZERO",
	"UNALIGNED",
	"NOCP",
	"INVPC",
	"INVSTATE",
	"UNDEFINSTR"
};
%% endif
%% if parameters.enable_hardfault_handler_log != "false"
const char *stack_frame_names[] = {
	"R0",
	"R1",
	"R2",
	"R3",
	"R12",
	"LR",
	"PC",
	"xPSR",
	%% if target is not cortex_m0
	"S0",
	"S1",
	"S2",
	"S3",
	"S4",
	"S5",
	"S6",
	"S7",
	"S8",
	"S9",
	"S10",
	"S11",
	"S12",
	"S13",
	"S14",
	"S15",
	"FPSCR",
	%% endif
	""
};
const char *exception_stack_frame = " ^-- exception stack frame\n";
%% endif

%% if parameters.enable_hardfault_handler_log != "false"
// ----------------------------------------------------------------------------
extern "C" void _hardFaultHandler(const uint32_t *ctx, const uint32_t *msp) __attribute__((noreturn, optimize("Os")));
extern "C" void _hardFaultHandler(const uint32_t *ctx, const uint32_t *msp)
{
#undef XPCC_LOG_LEVEL
#define XPCC_LOG_LEVEL	xpcc::log::ERROR
	// all CPU registers
	%% if target is cortex_m0
	const uint32_t& stacked_r8  = ctx[ 0];
	const uint32_t& stacked_r9  = ctx[ 1];
	const uint32_t& stacked_r10 = ctx[ 2];
	const uint32_t& stacked_r11 = ctx[ 3];
	const uint32_t& stacked_r12 = ctx[ 4];
	const uint32_t& stacked_lr  = ctx[ 5]; // possibly invalid!
	const uint32_t& stacked_pc  = ctx[ 6]; // possibly invalid!
	const uint32_t& stacked_psr = ctx[ 7]; // possibly invalid!

	const uint32_t& stacked_r0  = ctx[ 8];
	const uint32_t& stacked_r1  = ctx[ 9];
	const uint32_t& stacked_r2  = ctx[10];
	const uint32_t& stacked_r3  = ctx[11];
	const uint32_t& stacked_r4  = ctx[12];
	const uint32_t& stacked_r5  = ctx[13];
	const uint32_t& stacked_r6  = ctx[14];
	const uint32_t& stacked_r7  = ctx[15];
	%% else
	// all fault registers
	const uint32_t& shcrs = ctx[ 0];
	const uint32_t& cfsr  = ctx[ 1];
	const uint32_t& hfsr  = ctx[ 2];
	const uint32_t& dfsr  = ctx[ 3];
	const uint32_t& mmar  = ctx[ 4];
	const uint32_t& bfar  = ctx[ 5];
	const uint32_t& afsr  = ctx[ 6];

	const uint32_t& stacked_r8  = ctx[ 7];
	const uint32_t& stacked_r9  = ctx[ 8];
	const uint32_t& stacked_r10 = ctx[ 9];
	const uint32_t& stacked_r11 = ctx[10];
	const uint32_t& stacked_r12 = ctx[11];
	const uint32_t& stacked_lr  = ctx[12]; // possibly invalid!
	const uint32_t& stacked_pc  = ctx[13]; // possibly invalid!
	const uint32_t& stacked_psr = ctx[14]; // possibly invalid!

	const uint32_t& stacked_r0  = ctx[15];
	const uint32_t& stacked_r1  = ctx[16];
	const uint32_t& stacked_r2  = ctx[17];
	const uint32_t& stacked_r3  = ctx[18];
	const uint32_t& stacked_r4  = ctx[19];
	const uint32_t& stacked_r5  = ctx[20];
	const uint32_t& stacked_r6  = ctx[21];
	const uint32_t& stacked_r7  = ctx[22];
	%% endif

	xpcc::stm32::{{ uart ~ id }}::discardTransmitBuffer();

	// Infinite loop
	%% if parameters.enable_hardfault_handler_led
	volatile uint32_t ledCounter = 1;
	_initHardFaultHandlerLed();
	%% endif

	uint32_t logCounter = 1;

	while(1)
	{
	%% if parameters.enable_hardfault_handler_led
		if (--ledCounter == 0)
		{
			ledCounter = xpcc::clock::fcpu / 20;

			_toggleHardFaultHandlerLed();
		}
	%% endif

		if (--logCounter == 0)
		{
			logCounter = xpcc::clock::fcpu;

	%% if target is not cortex_m0
			// isolate the fault registers
			uint16_t usage_fault = ((cfsr & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos) & usage_fault_mask;
			uint8_t    bus_fault = ((cfsr & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos) &   bus_fault_mask;
			uint8_t    mem_fault = ((cfsr & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos) &   mem_fault_mask;

			bool is_mmar_valid = (cfsr & (1 <<  7));
			bool is_bfar_valid = (cfsr & (1 << 15));

			bool is_stack_overflow = (bus_fault and not usage_fault and not mem_fault) and
									 (is_bfar_valid and not is_mmar_valid) and
									 (bfar < __stack_start) and (msp < &__main_stack_top);

			bool is_stack_underflow = (bus_fault and not usage_fault and not mem_fault) and
									  (is_bfar_valid and not is_mmar_valid) and
									  (bfar > __main_stack_top);

			bool is_stack_execution = (cfsr == 0x00010000) and
									  (stacked_pc == (uint32_t)&__stack_start);

			//bool is_floating_point_active = FPU->FPCCR & 1;
	%% else
			bool is_stack_execution = (stacked_pc == (uint32_t)&__stack_start);
			//constexpr bool is_floating_point_active = false;
			const bool is_stack_overflow = (msp < &__stack_start);
			constexpr bool is_stack_underflow = false;
	%% endif
			XPCC_LOG_ERROR.printf("\n\n\n####  Hard Fault Exception  ####\n\n"); flushUart();

			// search for the highest watermark level on the stack
			uint32_t *ii = ((uint32_t*)&__stack_start) + 1;
			uint32_t value = 0xE7FBE7FC;
			while((ii <= &__main_stack_top) and (*ii == value))
			{
				ii++;
				if (value > 0xE401E402) value -= 0x20002;
				else value = 0xE401E401;
			}
			const uint32_t *main_stack_end = ii;

			// print the entire main stack content and annotate it
			/*
			uint32_t *sp = (uint32_t*)&__main_stack_top;
			for (; sp >= main_stack_end; sp--)
			{
				XPCC_LOG_ERROR.printf("sp[0x%08lx] : 0x%08lx", sp, *sp); flushUart();

				// annotate the stack
				if (sp == &__main_stack_top) { XPCC_LOG_ERROR << " <-- __main_stack_top\n"; }
				else if (sp == (msp + (is_floating_point_active ? 26 : 8))) { XPCC_LOG_ERROR << " <-- main stack pointer\n"; }
				else if (sp < (msp + (is_floating_point_active ? 26 : 8)) and sp >= msp) { XPCC_LOG_ERROR.printf(" | %s\n", stack_frame_names[sp - msp]); }
				else if (sp == msp - 1) { XPCC_LOG_ERROR << exception_stack_frame; }
				else { XPCC_LOG_ERROR << '\n'; }
			}
			if (sp == msp - 1) { XPCC_LOG_ERROR << "                           "; XPCC_LOG_ERROR << exception_stack_frame; }
			*/
			XPCC_LOG_ERROR.printf("Main Stack Pointer: %p\n", msp + 8); flushUart();
			XPCC_LOG_ERROR.printf("Maximum Stack Usage: %u Bytes\n", (&__main_stack_top - main_stack_end)*4); flushUart();

			XPCC_LOG_ERROR << '\n';
			XPCC_LOG_ERROR.printf("r0 : 0x%08lx   r8  : 0x%08lx\n",   stacked_r0, stacked_r8);  flushUart();
			XPCC_LOG_ERROR.printf("r1 : 0x%08lx   r9  : 0x%08lx\n",   stacked_r1, stacked_r9);  flushUart();
			XPCC_LOG_ERROR.printf("r2 : 0x%08lx   r10 : 0x%08lx\n",   stacked_r2, stacked_r10); flushUart();
			XPCC_LOG_ERROR.printf("r3 : 0x%08lx   r11 : 0x%08lx\n",   stacked_r3, stacked_r11); flushUart();
			XPCC_LOG_ERROR.printf("r4 : 0x%08lx   r12 : 0x%08lx\n",   stacked_r4, stacked_r12); flushUart();
			XPCC_LOG_ERROR.printf("r5 : 0x%08lx   lr  : 0x%08lx%s\n", stacked_r5, stacked_lr,  (is_stack_overflow or is_stack_underflow) ? invalid : valid); flushUart();
			XPCC_LOG_ERROR.printf("r6 : 0x%08lx   pc  : 0x%08lx%s\n", stacked_r6, stacked_pc,  (is_stack_overflow or is_stack_underflow) ? invalid : valid); flushUart();
			XPCC_LOG_ERROR.printf("r7 : 0x%08lx   psr : 0x%08lx%s\n", stacked_r7, stacked_psr, (is_stack_overflow or is_stack_underflow) ? invalid : valid); flushUart();

	%% if target is not cortex_m0
			XPCC_LOG_ERROR << '\n';
			XPCC_LOG_ERROR.printf("SHCSR : 0x%08lx\n",   shcrs); flushUart();
			XPCC_LOG_ERROR.printf("CFSR  : 0x%08lx\n",   cfsr);  flushUart();
			XPCC_LOG_ERROR.printf("HFSR  : 0x%08lx\n",   hfsr);  flushUart();
			XPCC_LOG_ERROR.printf("DFSR  : 0x%08lx\n",   dfsr);  flushUart();
			XPCC_LOG_ERROR.printf("MMAR  : 0x%08lx%s\n", mmar, is_mmar_valid ? valid : invalid); flushUart();
			XPCC_LOG_ERROR.printf("BFAR  : 0x%08lx%s\n", bfar, is_bfar_valid ? valid : invalid); flushUart();
			XPCC_LOG_ERROR.printf("AFSR  : 0x%08lx\n",   afsr);  flushUart();
		%% if parameters.enable_hardfault_handler_log != "basic"
			XPCC_LOG_ERROR << '\n';
			if (mem_fault)
			{
				XPCC_LOG_ERROR.printf("Memory Manage Faults:"); flushUart();
				for(uint8_t index = 0, mask = 0x80; mask; mask >>= 1)
				{
					if (mem_fault_mask & mask)
					{
						if (mem_fault & mask) {
							XPCC_LOG_ERROR << ' ' << mem_fault_bits[index]; flushUart();
						}
						index++;
					}
				};
				XPCC_LOG_ERROR << '\n';
			}
			if (bus_fault)
			{
				XPCC_LOG_ERROR.printf("Bus Faults:"); flushUart();
				for(uint8_t index = 0, mask = 0x80; mask; mask >>= 1)
				{
					if (bus_fault_mask & mask)
					{
						if (bus_fault & mask) {
							XPCC_LOG_ERROR << ' ' << bus_fault_bits[index]; flushUart();
						}
						index++;
					}
				};
				XPCC_LOG_ERROR << '\n';
			}
			if (usage_fault)
			{
				XPCC_LOG_ERROR.printf("Usage Faults:"); flushUart();
				for(uint16_t index = 0, mask = 0x8000; mask; mask >>= 1)
				{
					if (usage_fault_mask & mask)
					{
						if (usage_fault & mask) {
							XPCC_LOG_ERROR << ' ' << usage_fault_bits[index]; flushUart();
						}
						index++;
					}
				};
				XPCC_LOG_ERROR << '\n';
			}
		%% endif
	%% endif
			if (is_stack_execution) { XPCC_LOG_ERROR << "  ### STACK EXECUTION ###\n"; flushUart(); }
			if (is_stack_overflow)  { XPCC_LOG_ERROR << "  ### STACK OVERFLOW  ###\n"; flushUart(); }
	%% if target is not cortex_m0
			if (is_stack_underflow) { XPCC_LOG_ERROR << "  ### STACK UNDERFLOW ###\n"; flushUart(); }
	%% endif
		}
	}
}
%% endif