Network on chip or network on a chip (NoC) is a communication subsystem on an integrated chip, typically between IP cores in a System on Chip. NoC technology applies networking theory and methods to on chip communications and brings notable improvements over the conventional bus and crossbar interconnections. NoC improves the scalability of system on chips, and the power efficiency of complex system on chips compared to other designs. A packet in NoC is injected by the following cases:-
- L1,L2 Cache misses.
- Coherence Transactions.
- Synchronisation.
L1,L2 cache miss occurs when a processing core is not able to find the required memory item in its L1 cache or its shared L2 cache. In this case the processing core tries to find the item in the shared memory of other nodes in the network. Coherence transactions are required when more than 1 node holds the value of a variable from a different node , and one of the nodes updates the value of variable , then this value has to be updated with all other nodes holding this value. Synchronisation between two nodes is required when a node will be using a value which is generated by another node , so both these nodes have to be synchronised.
Network on chip is an emerging paradigm for communications within large VLSI systems implemented on a single Silicon Chip. A NOC is constructed from multiple point-point data links interconnected by switches, such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches.
The BookSim simulator used in the code is forked from https://github.com/booksim/booksim2