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Cycles out of sync #477

Answered by rokath
thelison asked this question in Q&A
Jun 14, 2024 · 5 comments · 4 replies
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Are you going to use both: direct AND deferred output? That is possible, but I guess you are just wont the direct output via SEGGER_RTT. So I recommend to change #define TRICE_BUFFER TRICE_RING_BUFFER into #define TRICE_BUFFER TRICE_STATIC_BUFFER. That probably will solve your problem. When you write into the ring buffer without reading it, it will be filled and then the last Trices get overwritten. Because your Trice messages are all equal, there is no data garbage, just missing messages. Currently is work in progress (#462) to protect against such wrong use cases.

If you want also deferred output you need to call TriceTransfer() cyclicylly to serve deferred output.

Analyzing:

$ trice l …

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