board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308(:1)

Original-Subject: arm64: dts: rockchip: Add acodec node for rk3308
Change-Id: I76f4a877711d33620bdef295e9047bdba26d4da4
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
X-Armbian: Patch-File: board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308
X-Armbian: Patch-File-Counter: 1
X-Armbian: Patch-Rel-Directory: patch/kernel/archive/rockchip64-6.3
X-Armbian: Patch-Type: kernel
X-Armbian: Patch-Root-Type: core
X-Armbian: Patch-Sub-Type: common
X-Armbian: Original-Subject: arm64: dts: rockchip: Add acodec node for rk3308

arch/arm64/boot/dts/rockchip/rk3308.dtsi

@@ -547,7 +547,7 @@
 		clock-names = "pclk", "timer";
 		status = "disabled";
 	};
-		
+
 	saradc: saradc@ff1e0000 {
 		compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
 		reg = <0x0 0xff1e0000 0x0 0x100>;
@@ -932,6 +932,22 @@
 		assigned-clock-rates = <32768>;
 	};
 
+	acodec: acodec@ff560000 {
+		compatible = "rockchip,rk3308-codec";
+		reg = <0x0 0xff560000 0x0 0x10000>;
+		rockchip,grf = <&grf>;
+		rockchip,detect-grf = <&detect_grf>;
+		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				 			   <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_ACODEC>,
+			 			 <&cru SCLK_I2S2_8CH_TX_OUT>,
+			 		 	 <&cru SCLK_I2S2_8CH_RX_OUT>;
+		clock-names = "acodec", "mclk_tx", "mclk_rx";
+		resets = <&cru SRST_ACODEC_P>;
+		reset-names = "acodec-reset";
+		status = "disabled";
+};
+
 	gic: interrupt-controller@ff580000 {
 		compatible = "arm,gic-400";
 		reg = <0x0 0xff581000 0x0 0x1000>,