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board-rk3328-roc-pc-dts-ram-profile(:1)
Original-Subject: [ARCHEOLOGY] Add files via upload > X-Git-Archeology: - Revision 8fc20a15b12561e76e92d5bd29b5afd1c62f08ac: armbian/build@8fc20a1 > X-Git-Archeology: Date: Thu, 08 Oct 2020 01:56:28 -0400 > X-Git-Archeology: From: Tony <tonymckahan@gmail.com> > X-Git-Archeology: Subject: Add files via upload > X-Git-Archeology: > X-Git-Archeology: - Revision 2788adccedc25f12fc9e71e01a92863d97683979: armbian/build@2788adc > X-Git-Archeology: Date: Tue, 26 Jan 2021 21:22:04 +0100 > X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com> > X-Git-Archeology: Subject: Enable DMC for Station M1 in current and dev (#2575) > X-Git-Archeology: > X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: armbian/build@0cdffb2 > X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 > X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com> > X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) > X-Git-Archeology: > X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: armbian/build@34ae84f > X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 > X-Git-Archeology: From: amazingfate <liujianfeng1994@gmail.com> > X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 > X-Git-Archeology: X-Armbian: Patch-File: board-rk3328-roc-pc-dts-ram-profile X-Armbian: Patch-File-Counter: 1 X-Armbian: Patch-Rel-Directory: patch/kernel/archive/rockchip64-6.3 X-Armbian: Patch-Type: kernel X-Armbian: Patch-Root-Type: core X-Armbian: Patch-Sub-Type: common X-Armbian: Original-Subject: [ARCHEOLOGY] Add files via upload
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arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
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| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
| /* | ||
| * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd | ||
| * | ||
| */ | ||
| #include <dt-bindings/clock/rockchip-ddr.h> | ||
| #include <dt-bindings/memory/rk3328-dram.h> | ||
|
|
||
| / { | ||
| ddr_timing: ddr_timing { | ||
| /* CA de-skew, one step is 47.8ps, range 0-15 */ | ||
| ddr3a1_ddr4a9_de-skew = <0>; | ||
| ddr3a0_ddr4a10_de-skew = <0>; | ||
| ddr3a3_ddr4a6_de-skew = <1>; | ||
| ddr3a2_ddr4a4_de-skew = <1>; | ||
| ddr3a5_ddr4a8_de-skew = <0>; | ||
| ddr3a4_ddr4a5_de-skew = <2>; | ||
| ddr3a7_ddr4a11_de-skew = <0>; | ||
| ddr3a6_ddr4a7_de-skew = <2>; | ||
| ddr3a9_ddr4a0_de-skew = <1>; | ||
| ddr3a8_ddr4a13_de-skew = <0>; | ||
| ddr3a11_ddr4a3_de-skew = <2>; | ||
| ddr3a10_ddr4cs0_de-skew = <0>; | ||
| ddr3a13_ddr4a2_de-skew = <1>; | ||
| ddr3a12_ddr4ba1_de-skew = <0>; | ||
| ddr3a15_ddr4odt0_de-skew = <0>; | ||
| ddr3a14_ddr4a1_de-skew = <1>; | ||
| ddr3ba1_ddr4a15_de-skew = <0>; | ||
| ddr3ba0_ddr4bg0_de-skew = <0>; | ||
| ddr3ras_ddr4cke_de-skew = <0>; | ||
| ddr3ba2_ddr4ba0_de-skew = <1>; | ||
| ddr3we_ddr4bg1_de-skew = <1>; | ||
| ddr3cas_ddr4a12_de-skew = <0>; | ||
| ddr3ckn_ddr4ckn_de-skew = <5>; | ||
| ddr3ckp_ddr4ckp_de-skew = <5>; | ||
| ddr3cke_ddr4a16_de-skew = <1>; | ||
| ddr3odt0_ddr4a14_de-skew = <0>; | ||
| ddr3cs0_ddr4act_de-skew = <1>; | ||
| ddr3reset_ddr4reset_de-skew = <0>; | ||
| ddr3cs1_ddr4cs1_de-skew = <0>; | ||
| ddr3odt1_ddr4odt1_de-skew = <0>; | ||
|
|
||
| /* DATA de-skew | ||
| * RX one step is 25.1ps, range 0-15 | ||
| * TX one step is 47.8ps, range 0-15 | ||
| */ | ||
| cs0_dm0_rx_de-skew = <7>; | ||
| cs0_dm0_tx_de-skew = <8>; | ||
| cs0_dq0_rx_de-skew = <7>; | ||
| cs0_dq0_tx_de-skew = <8>; | ||
| cs0_dq1_rx_de-skew = <7>; | ||
| cs0_dq1_tx_de-skew = <8>; | ||
| cs0_dq2_rx_de-skew = <7>; | ||
| cs0_dq2_tx_de-skew = <8>; | ||
| cs0_dq3_rx_de-skew = <7>; | ||
| cs0_dq3_tx_de-skew = <8>; | ||
| cs0_dq4_rx_de-skew = <7>; | ||
| cs0_dq4_tx_de-skew = <8>; | ||
| cs0_dq5_rx_de-skew = <7>; | ||
| cs0_dq5_tx_de-skew = <8>; | ||
| cs0_dq6_rx_de-skew = <7>; | ||
| cs0_dq6_tx_de-skew = <8>; | ||
| cs0_dq7_rx_de-skew = <7>; | ||
| cs0_dq7_tx_de-skew = <8>; | ||
| cs0_dqs0_rx_de-skew = <6>; | ||
| cs0_dqs0p_tx_de-skew = <9>; | ||
| cs0_dqs0n_tx_de-skew = <9>; | ||
|
|
||
| cs0_dm1_rx_de-skew = <7>; | ||
| cs0_dm1_tx_de-skew = <7>; | ||
| cs0_dq8_rx_de-skew = <7>; | ||
| cs0_dq8_tx_de-skew = <8>; | ||
| cs0_dq9_rx_de-skew = <7>; | ||
| cs0_dq9_tx_de-skew = <7>; | ||
| cs0_dq10_rx_de-skew = <7>; | ||
| cs0_dq10_tx_de-skew = <8>; | ||
| cs0_dq11_rx_de-skew = <7>; | ||
| cs0_dq11_tx_de-skew = <7>; | ||
| cs0_dq12_rx_de-skew = <7>; | ||
| cs0_dq12_tx_de-skew = <8>; | ||
| cs0_dq13_rx_de-skew = <7>; | ||
| cs0_dq13_tx_de-skew = <7>; | ||
| cs0_dq14_rx_de-skew = <7>; | ||
| cs0_dq14_tx_de-skew = <8>; | ||
| cs0_dq15_rx_de-skew = <7>; | ||
| cs0_dq15_tx_de-skew = <7>; | ||
| cs0_dqs1_rx_de-skew = <7>; | ||
| cs0_dqs1p_tx_de-skew = <9>; | ||
| cs0_dqs1n_tx_de-skew = <9>; | ||
|
|
||
| cs0_dm2_rx_de-skew = <7>; | ||
| cs0_dm2_tx_de-skew = <8>; | ||
| cs0_dq16_rx_de-skew = <7>; | ||
| cs0_dq16_tx_de-skew = <8>; | ||
| cs0_dq17_rx_de-skew = <7>; | ||
| cs0_dq17_tx_de-skew = <8>; | ||
| cs0_dq18_rx_de-skew = <7>; | ||
| cs0_dq18_tx_de-skew = <8>; | ||
| cs0_dq19_rx_de-skew = <7>; | ||
| cs0_dq19_tx_de-skew = <8>; | ||
| cs0_dq20_rx_de-skew = <7>; | ||
| cs0_dq20_tx_de-skew = <8>; | ||
| cs0_dq21_rx_de-skew = <7>; | ||
| cs0_dq21_tx_de-skew = <8>; | ||
| cs0_dq22_rx_de-skew = <7>; | ||
| cs0_dq22_tx_de-skew = <8>; | ||
| cs0_dq23_rx_de-skew = <7>; | ||
| cs0_dq23_tx_de-skew = <8>; | ||
| cs0_dqs2_rx_de-skew = <6>; | ||
| cs0_dqs2p_tx_de-skew = <9>; | ||
| cs0_dqs2n_tx_de-skew = <9>; | ||
|
|
||
| cs0_dm3_rx_de-skew = <7>; | ||
| cs0_dm3_tx_de-skew = <7>; | ||
| cs0_dq24_rx_de-skew = <7>; | ||
| cs0_dq24_tx_de-skew = <8>; | ||
| cs0_dq25_rx_de-skew = <7>; | ||
| cs0_dq25_tx_de-skew = <7>; | ||
| cs0_dq26_rx_de-skew = <7>; | ||
| cs0_dq26_tx_de-skew = <7>; | ||
| cs0_dq27_rx_de-skew = <7>; | ||
| cs0_dq27_tx_de-skew = <7>; | ||
| cs0_dq28_rx_de-skew = <7>; | ||
| cs0_dq28_tx_de-skew = <7>; | ||
| cs0_dq29_rx_de-skew = <7>; | ||
| cs0_dq29_tx_de-skew = <7>; | ||
| cs0_dq30_rx_de-skew = <7>; | ||
| cs0_dq30_tx_de-skew = <7>; | ||
| cs0_dq31_rx_de-skew = <7>; | ||
| cs0_dq31_tx_de-skew = <7>; | ||
| cs0_dqs3_rx_de-skew = <7>; | ||
| cs0_dqs3p_tx_de-skew = <9>; | ||
| cs0_dqs3n_tx_de-skew = <9>; | ||
|
|
||
| cs1_dm0_rx_de-skew = <7>; | ||
| cs1_dm0_tx_de-skew = <8>; | ||
| cs1_dq0_rx_de-skew = <7>; | ||
| cs1_dq0_tx_de-skew = <8>; | ||
| cs1_dq1_rx_de-skew = <7>; | ||
| cs1_dq1_tx_de-skew = <8>; | ||
| cs1_dq2_rx_de-skew = <7>; | ||
| cs1_dq2_tx_de-skew = <8>; | ||
| cs1_dq3_rx_de-skew = <7>; | ||
| cs1_dq3_tx_de-skew = <8>; | ||
| cs1_dq4_rx_de-skew = <7>; | ||
| cs1_dq4_tx_de-skew = <8>; | ||
| cs1_dq5_rx_de-skew = <7>; | ||
| cs1_dq5_tx_de-skew = <8>; | ||
| cs1_dq6_rx_de-skew = <7>; | ||
| cs1_dq6_tx_de-skew = <8>; | ||
| cs1_dq7_rx_de-skew = <7>; | ||
| cs1_dq7_tx_de-skew = <8>; | ||
| cs1_dqs0_rx_de-skew = <6>; | ||
| cs1_dqs0p_tx_de-skew = <9>; | ||
| cs1_dqs0n_tx_de-skew = <9>; | ||
|
|
||
| cs1_dm1_rx_de-skew = <7>; | ||
| cs1_dm1_tx_de-skew = <7>; | ||
| cs1_dq8_rx_de-skew = <7>; | ||
| cs1_dq8_tx_de-skew = <8>; | ||
| cs1_dq9_rx_de-skew = <7>; | ||
| cs1_dq9_tx_de-skew = <7>; | ||
| cs1_dq10_rx_de-skew = <7>; | ||
| cs1_dq10_tx_de-skew = <8>; | ||
| cs1_dq11_rx_de-skew = <7>; | ||
| cs1_dq11_tx_de-skew = <7>; | ||
| cs1_dq12_rx_de-skew = <7>; | ||
| cs1_dq12_tx_de-skew = <8>; | ||
| cs1_dq13_rx_de-skew = <7>; | ||
| cs1_dq13_tx_de-skew = <7>; | ||
| cs1_dq14_rx_de-skew = <7>; | ||
| cs1_dq14_tx_de-skew = <8>; | ||
| cs1_dq15_rx_de-skew = <7>; | ||
| cs1_dq15_tx_de-skew = <7>; | ||
| cs1_dqs1_rx_de-skew = <7>; | ||
| cs1_dqs1p_tx_de-skew = <9>; | ||
| cs1_dqs1n_tx_de-skew = <9>; | ||
|
|
||
| cs1_dm2_rx_de-skew = <7>; | ||
| cs1_dm2_tx_de-skew = <8>; | ||
| cs1_dq16_rx_de-skew = <7>; | ||
| cs1_dq16_tx_de-skew = <8>; | ||
| cs1_dq17_rx_de-skew = <7>; | ||
| cs1_dq17_tx_de-skew = <8>; | ||
| cs1_dq18_rx_de-skew = <7>; | ||
| cs1_dq18_tx_de-skew = <8>; | ||
| cs1_dq19_rx_de-skew = <7>; | ||
| cs1_dq19_tx_de-skew = <8>; | ||
| cs1_dq20_rx_de-skew = <7>; | ||
| cs1_dq20_tx_de-skew = <8>; | ||
| cs1_dq21_rx_de-skew = <7>; | ||
| cs1_dq21_tx_de-skew = <8>; | ||
| cs1_dq22_rx_de-skew = <7>; | ||
| cs1_dq22_tx_de-skew = <8>; | ||
| cs1_dq23_rx_de-skew = <7>; | ||
| cs1_dq23_tx_de-skew = <8>; | ||
| cs1_dqs2_rx_de-skew = <6>; | ||
| cs1_dqs2p_tx_de-skew = <9>; | ||
| cs1_dqs2n_tx_de-skew = <9>; | ||
|
|
||
| cs1_dm3_rx_de-skew = <7>; | ||
| cs1_dm3_tx_de-skew = <7>; | ||
| cs1_dq24_rx_de-skew = <7>; | ||
| cs1_dq24_tx_de-skew = <8>; | ||
| cs1_dq25_rx_de-skew = <7>; | ||
| cs1_dq25_tx_de-skew = <7>; | ||
| cs1_dq26_rx_de-skew = <7>; | ||
| cs1_dq26_tx_de-skew = <7>; | ||
| cs1_dq27_rx_de-skew = <7>; | ||
| cs1_dq27_tx_de-skew = <7>; | ||
| cs1_dq28_rx_de-skew = <7>; | ||
| cs1_dq28_tx_de-skew = <7>; | ||
| cs1_dq29_rx_de-skew = <7>; | ||
| cs1_dq29_tx_de-skew = <7>; | ||
| cs1_dq30_rx_de-skew = <7>; | ||
| cs1_dq30_tx_de-skew = <7>; | ||
| cs1_dq31_rx_de-skew = <7>; | ||
| cs1_dq31_tx_de-skew = <7>; | ||
| cs1_dqs3_rx_de-skew = <7>; | ||
| cs1_dqs3p_tx_de-skew = <9>; | ||
| cs1_dqs3n_tx_de-skew = <9>; | ||
| }; | ||
| }; |