overlays-04-add-rk3318-box-wlan-ap6334(:1)

Original-Subject: rk3318-box: add device tree overlay to support AP6334 and clones
None
X-Armbian: Patch-File: overlays-04-add-rk3318-box-wlan-ap6334
X-Armbian: Patch-File-Counter: 1
X-Armbian: Patch-Rel-Directory: patch/kernel/archive/rockchip64-6.1
X-Armbian: Patch-Type: kernel
X-Armbian: Patch-Root-Type: core
X-Armbian: Patch-Sub-Type: common
X-Armbian: Original-Subject: rk3318-box: add device tree overlay to support AP6334 and clones

arch/arm64/boot/dts/rockchip/overlay/Makefile

@@ -12,7 +12,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
 	rockchip-dwc3-0-host.dtbo \
 	rockchip-w1-gpio.dtbo \
 	rockchip-rk3318-box-led-conf1.dtbo \
-	rockchip-rk3318-box-emmc-ddr.dtbo
+	rockchip-rk3318-box-emmc-ddr.dtbo \
+	rockchip-rk3318-box-wlan-ap6334.dtbo
 
 scr-$(CONFIG_ARCH_ROCKCHIP) += \
        rockchip-fixup.scr

arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays

@@ -129,3 +129,8 @@ YX_RK3328 and clones
 Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
 nowadays support DDR mode, but its reliability heavily depends upon the quality
 of board wiring
+
+### rk3318-box-wlan-ap6334
+
+Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
+wifi chip and clones

arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts

@@ -0,0 +1,117 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+	fragment@0 {
+		target = <&sdio>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			//sd-uhs-ddr50;
+
+			brcmf_sdio: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <4>;
+				interrupt-parent = <&gpio1>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake>;
+			};
+
+		};
+	};
+
+	fragment@1 {
+		target = <&sdio_ext>;
+		__overlay__ {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			//sd-uhs-ddr50;
+
+			brcmf_ext: wifi@1 {
+				reg = <1>;
+				compatible = "brcm,bcm4329-fmac";
+				//brcm,drive-strength = <8>;
+				interrupt-parent = <&gpio3>;
+				interrupt-names = "host_wake";
+				interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdio_host_wake_ext>;
+			};
+
+		};
+	};
+
+	fragment@2 {
+		target = <&uart0>;
+		__overlay__ {
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+			bluetooth {
+				compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt";
+				max-speed = <4000000>;
+				shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+				device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+				//host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+				vbat-supply = <&vcc_io>;
+				vddio-supply = <&vcc_18>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+				/*
+				interrupt-names = "host-wakeup";
+				interrupt-parent = <&gpio1>;
+				interrupts = <RK_PD2 IRQ_TYPE_NONE>;
+				*/
+				brcm,bt-pcm-int-params = [01 02 00 01 01];
+			};
+
+		};
+
+	};
+
+	fragment@3 {
+		target = <&pinctrl>;
+		__overlay__ {
+
+			bluetooth {
+
+
+				bt_reg_on_h: bt-enable {
+					rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>;
+				};
+
+				bt_device_wake_l: bt-device-wake {
+					rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+				};
+
+				bt_host_wake_l: bt-host-wake {
+					rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+				};
+
+			};
+
+		};
+	};
+
+};