rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay(:1)

Original-Subject: [ARCHEOLOGY] rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351)
> X-Git-Archeology: > recovered message: > * build: kernel: rockchip64-[current,edge]: add pcie bus scan delay patches
> X-Git-Archeology: > recovered message: > These are needed for cards like the LSI SAS2008 which needs a little
> X-Git-Archeology: > recovered message: > extra time to initialize or they'll cause a kernel panic.
> X-Git-Archeology: > recovered message: > References:
> X-Git-Archeology: > recovered message: > https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
> X-Git-Archeology: > recovered message: > https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0022-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch
> X-Git-Archeology: > recovered message: > * config: linux-rockchip64-[current,edge]: enable lsi sata/sas support
> X-Git-Archeology: - Revision 7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a: armbian/build@7be9e8b
> X-Git-Archeology:   Date: Thu, 16 Dec 2021 05:17:33 -0500
> X-Git-Archeology:   From: Dan Pasanen <dan.pasanen@gmail.com>
> X-Git-Archeology:   Subject: rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351)
> X-Git-Archeology: 
> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: armbian/build@34ae84f
> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
> X-Git-Archeology: 
X-Armbian: Patch-File: rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay
X-Armbian: Patch-File-Counter: 1
X-Armbian: Patch-Rel-Directory: patch/kernel/archive/rockchip64-6.3
X-Armbian: Patch-Type: kernel
X-Armbian: Patch-Root-Type: core
X-Armbian: Patch-Sub-Type: common
X-Armbian: Original-Subject: [ARCHEOLOGY] rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351)

Documentation/admin-guide/kernel-parameters.txt

@@ -4388,6 +4388,14 @@
 		nomsi	Do not use MSI for native PCIe PME signaling (this makes
 			all PCIe root ports use INTx for all services).
 
+	pcie_rockchip_host.bus_scan_delay=	[PCIE] Delay in ms before
+			scanning PCIe bus in Rockchip PCIe host driver. Some PCIe
+			cards seem to need delays that can be several hundred ms.
+			If set to greater than or equal to 0 this parameter will
+			override delay that can be set in device tree.
+			Values less than 0 mean that this parameter is ignored.
+			default=-1
+
 	pcmv=		[HW,PCMCIA] BadgePAD 4
 
 	pd_ignore_unused

drivers/pci/controller/pcie-rockchip-host.c

@@ -24,6 +24,7 @@
 #include <linux/kernel.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
+#include <linux/moduleparam.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/of_pci.h>
@@ -38,6 +39,9 @@
 #include "../pci.h"
 #include "pcie-rockchip.h"
 
+static int bus_scan_delay = -1;
+module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO);
+
 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
 {
 	u32 status;
@@ -932,6 +936,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct pci_host_bridge *bridge;
 	int err;
+	u32 delay = 0;
 
 	if (!dev->of_node)
 		return -ENODEV;
@@ -981,6 +986,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	bridge->sysdata = rockchip;
 	bridge->ops = &rockchip_pcie_ops;
 
+	/* Checking if bus scan delay was given from command line and prefer
+	 * that over the value in device tree (which defaults to 0 if not set).
+	 */
+	if (bus_scan_delay >= 0) {
+		delay = bus_scan_delay;
+		dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay);
+	} else {
+		delay = rockchip->bus_scan_delay;
+		dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay);
+	}
+	/* Workaround for some devices crashing on pci_host_probe / pci_scan_root_bus_bridge
+	 * calls: sleep a bit before bus scan. Call trace gets to rockchip_pcie_rd_conf when
+	 * trying to read vendor id (pci_bus_generic_read_dev_vendor_id is in call stack)
+	 * before panicing. I have no idea why this works or what causes the panic. I just
+	 * found this hack by luck when trying to "make it break differently if possible".
+	 */
+	if (delay > 0) {
+		msleep(delay);
+	}
+
 	err = rockchip_pcie_setup_irq(rockchip);
 	if (err)
 		goto err_remove_irq_domain;

drivers/pci/controller/pcie-rockchip.c

@@ -149,6 +149,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 		return PTR_ERR(rockchip->clk_pcie_pm);
 	}
 
+	err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay);
+	if (err) {
+		dev_info(dev, "no bus scan delay, default to 0 ms\n");
+		rockchip->bus_scan_delay = 0;
+	}
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);

drivers/pci/controller/pcie-rockchip.h

@@ -299,6 +299,8 @@ struct rockchip_pcie {
 	phys_addr_t msg_bus_addr;
 	bool is_rc;
 	struct resource *mem_res;
+	/* Bus scan delay is a workaround for some pcie devices causing crashes */
+	u32 bus_scan_delay;
 };
 
 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)