refactor: change the name of HardwareCounter to PerformanceCouneter

Processor/Project/Synplify/ver2017-03.prj

@@ -136,8 +136,8 @@ add_file -verilog -vlog_std sysv "../../Src/Primitives/Picker.sv"
 add_file -verilog -vlog_std sysv "../../Src/Primitives/Multiplier.sv"
 add_file -verilog -vlog_std sysv "../../Src/Debug/Debug.sv"
 add_file -verilog -vlog_std sysv "../../Src/Debug/DebugIF.sv"
-add_file -verilog -vlog_std sysv "../../Src/Debug/HardwareCounter.sv"
-add_file -verilog -vlog_std sysv "../../Src/Debug/HardwareCounterIF.sv"
+add_file -verilog -vlog_std sysv "../../Src/Debug/PerformanceCounter.sv"
+add_file -verilog -vlog_std sysv "../../Src/Debug/PerformanceCounterIF.sv"
 add_file -verilog -vlog_std sysv "../../Src/Memory/ControlQueue.sv"
 add_file -verilog -vlog_std sysv "../../Src/Memory/Axi4LiteControlRegisterIF.sv"
 add_file -verilog -vlog_std sysv "../../Src/Memory/Axi4LiteControlRegister.sv"

Processor/Src/Core.sv

@@ -43,7 +43,7 @@ output
     // --- For Debug
     //
     DebugIF debugIF( clk, rst );
-    HardwareCounterIF hwCounterIF( clk, rst );
+    PerformanceCounterIF perfCounterIF( clk, rst );
 
     assign debugRegister = debugIF.debugRegister;
 
@@ -56,7 +56,7 @@ output
 `endif
 
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
-    HardwareCounter hwCounter(hwCounterIF, debugIF);
+    PerformanceCounter perfCounter(perfCounterIF, debugIF);
 `endif
 
     //
@@ -133,11 +133,11 @@ output
         PC pc( npStageIF );
         BTB btb( npStageIF, ifStageIF );
         BranchPredictor brPred( npStageIF, ifStageIF, ctrlIF );
-    FetchStage ifStage( ifStageIF, npStageIF, ctrlIF, debugIF, hwCounterIF );
+    FetchStage ifStage( ifStageIF, npStageIF, ctrlIF, debugIF, perfCounterIF );
         ICache iCache( npStageIF, ifStageIF, cacheSystemIF );
 
     PreDecodeStage pdStage( pdStageIF, ifStageIF, ctrlIF, debugIF );
-    DecodeStage idStage( idStageIF, pdStageIF, ctrlIF, debugIF, hwCounterIF );
+    DecodeStage idStage( idStageIF, pdStageIF, ctrlIF, debugIF, perfCounterIF );
 
     RenameStage rnStage( rnStageIF, idStageIF, renameLogicIF, activeListIF, schedulerIF, loadStoreUnitIF, recoveryManagerIF, ctrlIF, debugIF );
         RenameLogic renameLogic( renameLogicIF, activeListIF, recoveryManagerIF );
@@ -174,12 +174,12 @@ output
     MemoryIssueStage memIsStage( memIsStageIF, scStageIF, schedulerIF, recoveryManagerIF, mulDivUnitIF, ctrlIF, debugIF );
     MemoryRegisterReadStage memRrStage( memRrStageIF, memIsStageIF,loadStoreUnitIF, mulDivUnitIF, registerFileIF, bypassNetworkIF, recoveryManagerIF, ctrlIF, debugIF );
     MemoryExecutionStage memExStage( memExStageIF, memRrStageIF, loadStoreUnitIF, cacheFlushManagerIF, mulDivUnitIF, bypassNetworkIF, recoveryManagerIF, ctrlIF, csrUnitIF, debugIF );
-    MemoryTagAccessStage mtStage( mtStageIF, memExStageIF, schedulerIF, loadStoreUnitIF, mulDivUnitIF, recoveryManagerIF, ctrlIF, debugIF, hwCounterIF );
+    MemoryTagAccessStage mtStage( mtStageIF, memExStageIF, schedulerIF, loadStoreUnitIF, mulDivUnitIF, recoveryManagerIF, ctrlIF, debugIF, perfCounterIF );
     MemoryAccessStage maStage( maStageIF, mtStageIF, loadStoreUnitIF, mulDivUnitIF, bypassNetworkIF, ioUnitIF, recoveryManagerIF, ctrlIF, debugIF );
         LoadStoreUnit loadStoreUnit( loadStoreUnitIF, ctrlIF );
         LoadQueue loadQueue( loadStoreUnitIF, recoveryManagerIF );
         StoreQueue storeQueue( loadStoreUnitIF, recoveryManagerIF );
-        StoreCommitter storeCommitter(loadStoreUnitIF, recoveryManagerIF, ioUnitIF, debugIF, hwCounterIF);
+        StoreCommitter storeCommitter(loadStoreUnitIF, recoveryManagerIF, ioUnitIF, debugIF, perfCounterIF);
         DCache dCache( loadStoreUnitIF, cacheSystemIF, ctrlIF );
     MemoryRegisterWriteStage memRwStage( /*memRwStageIF,*/ maStageIF, registerFileIF, activeListIF, recoveryManagerIF, ctrlIF, debugIF );
 
@@ -191,9 +191,9 @@ output
 `endif
     // A commitment stage generates a flush signal and this is send to scheduler.
     CommitStage cmStage( cmStageIF, renameLogicIF, activeListIF, loadStoreUnitIF, recoveryManagerIF, csrUnitIF, debugIF );
-        RecoveryManager recoveryManager( recoveryManagerIF, activeListIF, csrUnitIF, ctrlIF, hwCounterIF );
+        RecoveryManager recoveryManager( recoveryManagerIF, activeListIF, csrUnitIF, ctrlIF, perfCounterIF );
 
-    CSR_Unit csrUnit(csrUnitIF, hwCounterIF);
+    CSR_Unit csrUnit(csrUnitIF, perfCounterIF);
     CacheFlushManager cacheFlushManager( cacheFlushManagerIF, cacheSystemIF );
     InterruptController interruptCtrl(csrUnitIF, ctrlIF, npStageIF, recoveryManagerIF);
     IO_Unit ioUnit(ioUnitIF, csrUnitIF);

Processor/Src/Debug/DebugIF.sv

@@ -279,7 +279,7 @@ interface DebugIF( input logic clk, rst );
         cmReg
     );
 
-    modport HardwareCounter (
+    modport PerformanceCounter (
     output 
         perfCounter
     );
@@ -400,7 +400,7 @@ interface DebugIF( input logic clk, rst );
         output lastCommittedPC
     );
 
-    modport HardwareCounter (
+    modport PerformanceCounter (
         input clk
     );
 `endif

Processor/Src/Debug/HardwareCounter.sv → Processor/Src/Debug/PerformanceCounter.sv

@@ -6,9 +6,9 @@
 import BasicTypes::*;
 import DebugTypes::*;
 
-module HardwareCounter (
-    HardwareCounterIF.HardwareCounter port,
-    DebugIF.HardwareCounter debug
+module PerformanceCounter (
+    PerformanceCounterIF.PerformanceCounter port,
+    DebugIF.PerformanceCounter debug
 );
     PerfCounterPath cur, next;
     always_ff @(posedge port.clk) begin
@@ -38,16 +38,16 @@ module HardwareCounter (
     end
 
 
-endmodule : HardwareCounter
+endmodule : PerformanceCounter
 
 `else
 
-module HardwareCounter (
-    HardwareCounterIF.HardwareCounter port
+module PerformanceCounter (
+    PerformanceCounterIF.PerformanceCounter port
 );
     always_comb begin
         port.perfCounter = '0; // Suppressing warning.
     end
-endmodule : HardwareCounter
+endmodule : PerformanceCounter
 
 `endif

Processor/Src/Debug/HardwareCounterIF.sv → Processor/Src/Debug/PerformanceCounterIF.sv

@@ -3,13 +3,13 @@
 
 
 //
-// --- HardwareCounterIF
+// --- PerformanceCounterIF
 //
 
 import BasicTypes::*;
 import DebugTypes::*;
 
-interface HardwareCounterIF( input logic clk, rst );
+interface PerformanceCounterIF( input logic clk, rst );
 
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
 
@@ -31,7 +31,7 @@ interface HardwareCounterIF( input logic clk, rst );
     logic branchPredMiss;
     logic branchPredMissDetectedOnDecode;
 
-    modport HardwareCounter (
+    modport PerformanceCounter (
     input
         clk,
         rst,
@@ -81,7 +81,7 @@ interface HardwareCounterIF( input logic clk, rst );
     // Dummy to suppress warning.
     PerfCounterPath perfCounter;
 
-    modport HardwareCounter (
+    modport PerformanceCounter (
     input
         clk,
     output
@@ -98,4 +98,4 @@ interface HardwareCounterIF( input logic clk, rst );
 `endif
 
 
-endinterface : HardwareCounterIF
+endinterface : PerformanceCounterIF

Processor/Src/LoadStoreUnit/StoreCommitter.sv

@@ -20,7 +20,7 @@ module StoreCommitter(
     RecoveryManagerIF.StoreCommitter recovery,
     IO_UnitIF.StoreCommitter ioUnit,
     DebugIF.StoreCommitter debug,
-    HardwareCounterIF.StoreCommitter hwCounter
+    PerformanceCounterIF.StoreCommitter perfCounter
 );
 
     // State machine
@@ -315,7 +315,7 @@ module StoreCommitter(
 
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
         for (int i = 0; i < STORE_ISSUE_WIDTH; i++) begin
-            hwCounter.storeMiss[i] = i == 0 ? finishWriteBack : FALSE;  // Only supports a single store port 
+            perfCounter.storeMiss[i] = i == 0 ? finishWriteBack : FALSE;  // Only supports a single store port 
         end
 `endif
     end

Processor/Src/Makefiles/CoreSources.inc.mk

@@ -162,8 +162,8 @@ MODULES = \
 	Primitives/Divider.sv \
 	Debug/Debug.sv \
 	Debug/DebugIF.sv \
-	Debug/HardwareCounter.sv \
-	Debug/HardwareCounterIF.sv \
+	Debug/PerformanceCounter.sv \
+	Debug/PerformanceCounterIF.sv \
 	Memory/Axi4LiteControlRegisterIF.sv \
 	Memory/Axi4LiteControlRegister.sv \
 	Memory/ControlQueue.sv \

Processor/Src/Makefiles/TestCommands.inc.mk

@@ -40,7 +40,7 @@ LEVEL1_TESTS = \
 #	test-RV32I-MisalignedMemAccess \
 
 # アドレス変更に伴い，一時的に無効に
-#	test-HardwareCounter \
+#	test-PerformanceCounter \
 
 LEVEL2_TESTS = \
 	test-riscv-compliance \
@@ -188,8 +188,8 @@ test-Coremark:
 	$(RUN_TEST_OMIT_MSG) Verification/TestCode/Coremark/Coremark
 test-Coremark_for_RV32I:
 	$(RUN_TEST_OMIT_MSG) Verification/TestCode/Coremark/Coremark_for_RV32I
-test-HardwareCounter:
-	$(RUN_TEST_OMIT_MSG) Verification/TestCode/C/HardwareCounter
+test-PerformanceCounter:
+	$(RUN_TEST_OMIT_MSG) Verification/TestCode/C/PerformanceCounter
 test-Dhrystone:
 	$(RUN_TEST_OMIT_MSG) Verification/TestCode/Dhrystone/Dhrystone
 test-Dhrystone-for-contest:

Processor/Src/Pipeline/DecodeStage.sv

@@ -71,7 +71,7 @@ module DecodeStage(
     PreDecodeStageIF.NextStage prev,
     ControllerIF.DecodeStage ctrl,
     DebugIF.DecodeStage debug,
-    HardwareCounterIF.DecodeStage hwCounter
+    PerformanceCounterIF.DecodeStage perfCounter
 );
     // --- Pipeline registers
     DecodeStageRegPath pipeReg[DECODE_WIDTH];
@@ -282,7 +282,7 @@ module DecodeStage(
         port.nextStage = nextStage;
 
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
-        hwCounter.branchPredMissDetectedOnDecode = complete && flushTriggered && !clear;
+        perfCounter.branchPredMissDetectedOnDecode = complete && flushTriggered && !clear;
 `endif
         // Debug Register
 `ifndef RSD_DISABLE_DEBUG_REGISTER

Processor/Src/Pipeline/FetchStage/FetchStage.sv

@@ -16,7 +16,7 @@ module FetchStage(
     NextPCStageIF.NextStage prev,
     ControllerIF.FetchStage ctrl,
     DebugIF.FetchStage debug,
-    HardwareCounterIF.FetchStage hwCounter
+    PerformanceCounterIF.FetchStage perfCounter
 );
 
     // Pipeline Control
@@ -60,7 +60,7 @@ module FetchStage(
 
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
         // Stall can be caused by another reason from an i-cache miss.
-        hwCounter.icMiss = beginStall && pipeReg[0].valid && !port.icReadHit[0];
+        perfCounter.icMiss = beginStall && pipeReg[0].valid && !port.icReadHit[0];
 `endif
     end
 

Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv

@@ -36,7 +36,7 @@ module MemoryTagAccessStage(
     RecoveryManagerIF.MemoryTagAccessStage recovery,
     ControllerIF.MemoryTagAccessStage ctrl,
     DebugIF.MemoryTagAccessStage debug,
-    HardwareCounterIF.MemoryTagAccessStage hwCounter
+    PerformanceCounterIF.MemoryTagAccessStage perfCounter
 );
 
     MemoryTagAccessStageRegPath pipeReg[MEM_ISSUE_WIDTH];
@@ -540,7 +540,7 @@ module MemoryTagAccessStage(
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
         for ( int i = 0; i < LOAD_ISSUE_WIDTH; i++ ) begin
             // Record misses only when a MSHR entry is allocated.
-            hwCounter.loadMiss[i] =
+            perfCounter.loadMiss[i] =
                 ldUpdate[i] && isLoad[i] && ldMSHR_Allocated[i];
         end
 `endif

Processor/Src/Privileged/CSR_Unit.sv

@@ -16,7 +16,7 @@ import SchedulerTypes::*;
 
 module CSR_Unit(
     CSR_UnitIF.CSR_Unit port,
-    HardwareCounterIF.CSR hwCounter
+    PerformanceCounterIF.CSR perfCounter
 );
 
     CSR_BodyPath csrReg, csrNext;
@@ -60,9 +60,9 @@ module CSR_Unit(
             CSR_NUM_MCYCLE:   rv = csrReg.mcycle;
             CSR_NUM_MINSTRET: rv = csrReg.minstret;
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
-            CSR_NUM_MHPMCOUNTER3: rv = hwCounter.perfCounter.numLoadMiss;
-            CSR_NUM_MHPMCOUNTER4: rv = hwCounter.perfCounter.numStoreMiss;
-            CSR_NUM_MHPMCOUNTER5: rv = hwCounter.perfCounter.numBranchPredMiss;
+            CSR_NUM_MHPMCOUNTER3: rv = perfCounter.perfCounter.numLoadMiss;
+            CSR_NUM_MHPMCOUNTER4: rv = perfCounter.perfCounter.numStoreMiss;
+            CSR_NUM_MHPMCOUNTER5: rv = perfCounter.perfCounter.numBranchPredMiss;
 `endif
             default:          rv = '0;
         endcase 

Processor/Src/Recovery/RecoveryManager.sv

@@ -25,7 +25,7 @@ module RecoveryManager(
     ActiveListIF.RecoveryManager activeList,
     CSR_UnitIF.RecoveryManager csrUnit,
     ControllerIF.RecoveryManager ctrl,
-    HardwareCounterIF.RecoveryManager hwCounter
+    PerformanceCounterIF.RecoveryManager perfCounter
 );
     typedef struct packed
     {
@@ -212,11 +212,11 @@ module RecoveryManager(
 
         // Hardware Counter
 `ifndef RSD_DISABLE_HARDWARE_COUNTER
-        hwCounter.storeLoadForwardingFail =
+        perfCounter.storeLoadForwardingFail =
             regState.phase == PHASE_RECOVER_0 && (regState.refetchType == REFETCH_TYPE_THIS_PC);
-        hwCounter.memDepPredMiss =
+        perfCounter.memDepPredMiss =
             regState.phase == PHASE_RECOVER_0 && (regState.refetchType inside {REFETCH_TYPE_NEXT_PC, REFETCH_TYPE_STORE_NEXT_PC});
-        hwCounter.branchPredMiss =
+        perfCounter.branchPredMiss =
             regState.phase == PHASE_RECOVER_0 && (regState.refetchType == REFETCH_TYPE_BRANCH_TARGET);
 `endif
     end