More RISC-V instructions in core::arch

[luojia65]

This pull request includes:

• Hypervisor extension, including memory management insturctions and virtual machine memory load and store instructions
• Supervisor memory management, including address translation fence insturctions (important for Rust kernel development) and cache invalidation insturctions
• Non privileged instructions FENCE.I, NOP and WFI

Module riscv64 is added to include RV64 only virtual machine memory instructions. RV64 supports all RV32 virtual machine instructions, it's implemented like:

    pub mod riscv64 {
        pub use crate::core_arch::riscv::*;
        pub use crate::core_arch::riscv64::*;
    }

(Edit: implemented like pub use crate::core_arch::riscv32::*; etc)

Most of implemented functions are marked as unsafe. That's because these functions either load or store effectively into raw pointer (hlv, hlvx and hsv instructions), or would effect how the RISC-V core handles page memory translation (memory management fences and cache invalidations).

Specifically, here's a list of implemented instruction functions from updated RISC-V core arch module:

Marked as draft: more polishing on documents(done), and decide whether #[must_use] is necessary on virtual machine memory loads.(ref: ptr::read & ptr::write, does not put #[must_use] by now)

[rust-highfive]

r? @Amanieu

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[Amanieu]

LGTM other than the module name issue.

[luojia65]

I modified riscv to riscv32.

r? @Amanieu

[Amanieu]

All of the asm! blocks here should use nostack since they don't push anything to the stack.

Additionally:

• Most should use nomem, except for loads which should use readonly and stores which should use neither.

[luojia65]

Thanks, I'll check it out.
There are many privileged memory fences as well, I'd also figure it out in these intrinsic functions.

[Amanieu]

Good point about the fences, those should not use nomem/readonly because they need to act as a compiler fence.

[Amanieu]

Perhaps calling this riscv_shared (like arm_shared) makes more sense?

[luojia65]

That makes sense, it would be a more common module system design.

[luojia65]

Hello! I renamed internal shared riscv module to riscv_shared, and modified asm! options under following rules:

• Trivial no-op instruction (NOP), wait-for-interrupt (WFI): options(nomem, nostack)
• Unprivileged fences (FENCE.I), privileged fences (SFENCE.*, SINVAL.*, HFENCE.*, HINVAL.*): options(nostack)
• Hypervisor loads (HLV.*, HLVX.*): options(readonly, nostack)
• Hypervisor stores (HSV.*): options(nostack)

r? @Amanieu