Merge pull request #18 from luojia65/main

Adapts to RustSBI 0.2.2

CHANGELOG.md

@@ -9,10 +9,20 @@ to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ### Added
 
+### Modified
+
+## [0.1.1] - 2022-03-23
+
+### Added
+
+- Adapts to RustSBI version 0.2.2, RISC-V SBI version 1.0.0 ratified
 - Handle possible failure of deref virtual address by machine trap detection
 
 ### Modified
 
+- Use Rust Edition 2021
+- Modify test kernel message
+
 ## [0.1.0] - 2022-02-13
 
 ### Added
@@ -23,6 +33,6 @@ to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 - Fixes on usage of CLINT peripheral, thanks to @duskmoon314
 - Numerous fixes to HSM module implementation, more documents
 
-[Unreleased]: https://github.com/rustsbi/rustsbi-qemu/compare/v0.1.0...HEAD
-
+[Unreleased]: https://github.com/rustsbi/rustsbi-qemu/compare/v0.1.1...HEAD
+[0.1.1]: https://github.com/rustsbi/rustsbi-qemu/compare/v0.1.0...v0.1.1
 [0.1.0]: https://github.com/rustsbi/rustsbi-qemu/releases/tag/v0.1.0

README.md

@@ -13,16 +13,15 @@ cargo qemu
 
 When running `cargo qemu`, the test kernel will build and run. Expected output should be:
 
-```
-[rustsbi] RustSBI version 0.2.0, adapting to RISC-V SBI v0.3
+[rustsbi] RustSBI version 0.2.2, adapting to RISC-V SBI v0.3
 .______       __    __      _______.___________.  _______..______   __
 |   _  \     |  |  |  |    /       |           | /       ||   _  \ |  |
 |  |_)  |    |  |  |  |   |   (----`---|  |----`|   (----`|  |_)  ||  |
 |      /     |  |  |  |    \   \       |  |      \   \    |   _  < |  |
 |  |\  \----.|  `--'  |.----)   |      |  |  .----)   |   |  |_)  ||  |
 | _| `._____| \______/ |_______/       |__|  |_______/    |______/ |__|
 
-[rustsbi] Implementation: RustSBI-QEMU Version 0.1.0
+[rustsbi] Implementation: RustSBI-QEMU Version 0.1.1
 [rustsbi-dtb] Hart count: cluster0 with 8 cores
 [rustsbi] misa: RV64ACDFIMSU
 [rustsbi] mideleg: ssoft, stimer, sext (0x222)
@@ -35,15 +34,15 @@ When running `cargo qemu`, the test kernel will build and run. Expected output s
 << Test-kernel: Hart id = 0, DTB physical address = 0x87000000
 >> Test-kernel: Testing base extension
 << Test-kernel: Base extension version: 1
-<< Test-kernel: SBI specification version: 3
+<< Test-kernel: SBI specification version: 1.0
 << Test-kernel: SBI implementation Id: 4
-<< Test-kernel: SBI implementation version: 200
+<< Test-kernel: SBI implementation version: 202
 << Test-kernel: Device mvendorid: 0
 << Test-kernel: Device marchid: 0
 << Test-kernel: Device mimpid: 0
 >> Test-kernel: Testing SBI instruction emulation
-<< Test-kernel: Current time: 17fc45
-<< Test-kernel: Time after operation: 187678
+<< Test-kernel: Current time: d78c9
+<< Test-kernel: Time after operation: da00f
 >> Test-kernel: Trigger illegal exception
 << Test-kernel: Value of scause: Exception(IllegalInstruction)
 << Test-kernel: Illegal exception delegate success
@@ -52,6 +51,7 @@ When running `cargo qemu`, the test kernel will build and run. Expected output s
 >> Hart 1 state return value: 4
 >> Hart 2 state return value: 4
 >> Hart 3 state return value: 1
+>> Hart 4 state return value: 0
 << Test-kernel: test for hart 0 success, wake another hart
 >> Wake hart 1, sbi return value 0
 >> Start test for hart 1, retentive suspend return value 0

rustsbi-qemu/Cargo.toml

@@ -1,19 +1,19 @@
 [package]
 name = "rustsbi-qemu"
-version = "0.1.0"
-edition = "2018"
+version = "0.1.1"
+edition = "2021"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-rustsbi = "0.2.1"
+rustsbi = "0.2.2"
 buddy_system_allocator = "0.8"
 lazy_static = { version = "1", features = ["spin_no_std"] }
 spin = "0.9"
 riscv = { git = "https://github.com/rust-embedded/riscv", rev = "dc0bc37e", features = ["inline-asm"] }
 device_tree = { git = "https://github.com/rcore-os/device_tree-rs/" }
-embedded-hal = "0.2.6"
+embedded-hal = "0.2.7"
 nb = "1"
 bitflags = "1"
 bit_field = "0.10"
-hashbrown = "0.11"
+hashbrown = "0.12"

rustsbi-qemu/src/execute.rs

@@ -3,12 +3,14 @@ use core::{
     pin::Pin,
 };
 
-use riscv::register::{mcause, mie, mip, scause::{Exception, Trap}};
-use riscv::register::scause::Interrupt;
+use riscv::register::{
+    mcause, mie, mip,
+    scause::{Exception, Interrupt, Trap},
+};
 
 use crate::feature;
 use crate::prv_mem::{self, SupervisorPointer};
-use crate::qemu_hsm::{HsmCommand, pause, QemuHsm};
+use crate::qemu_hsm::{pause, HsmCommand, QemuHsm};
 use crate::runtime::{MachineTrap, Runtime, SupervisorContext};
 
 pub fn execute_supervisor(supervisor_mepc: usize, hart_id: usize, a1: usize, hsm: QemuHsm) -> ! {
@@ -102,10 +104,7 @@ pub fn execute_supervisor(supervisor_mepc: usize, hart_id: usize, a1: usize, hsm
                     let clint = crate::clint::Clint::new(0x2000000 as *mut u8);
                     clint.clear_soft(hart_id); // Clear IPI
                     if feature::should_transfer_trap(ctx) {
-                        feature::do_transfer_trap(
-                            ctx,
-                            Trap::Interrupt(Interrupt::SupervisorSoft),
-                        )
+                        feature::do_transfer_trap(ctx, Trap::Interrupt(Interrupt::SupervisorSoft))
                     } else {
                         panic!("rustsbi-qemu: machine soft interrupt with no hart state monitor command")
                     }
@@ -140,7 +139,13 @@ fn fail_illegal_instruction(ctx: &mut SupervisorContext, ins: usize) -> ! {
 
 fn fail_cant_read_exception_address(ctx: &mut SupervisorContext, cause: mcause::Exception) -> ! {
     #[cfg(target_pointer_width = "64")]
-    panic!("can't read exception address, cause: {:?}, mepc: {:016x?}, context: {:016x?}", cause, ctx.mepc, ctx);
+    panic!(
+        "can't read exception address, cause: {:?}, mepc: {:016x?}, context: {:016x?}",
+        cause, ctx.mepc, ctx
+    );
     #[cfg(target_pointer_width = "32")]
-    panic!("can't read exception address, cause: {:?}, mepc: {:08x?}, context: {:08x?}", cause, ctx.mepc, ctx);
+    panic!(
+        "can't read exception address, cause: {:?}, mepc: {:08x?}, context: {:08x?}",
+        cause, ctx.mepc, ctx
+    );
 }

rustsbi-qemu/src/main.rs

@@ -64,7 +64,7 @@ extern "C" fn rust_main(hartid: usize, opqaue: usize) -> ! {
         init_clint();
         init_test_device();
         println!(
-            "[rustsbi] RustSBI version {}, adapting to RISC-V SBI v0.3",
+            "[rustsbi] RustSBI version {}, adapting to RISC-V SBI v1.0.0",
             rustsbi::VERSION
         );
         println!("{}", rustsbi::LOGO);
@@ -180,16 +180,14 @@ fn set_pmp() {
     // A = NA4(naturally aligned 4-byte region, 2), only support a 4-byte pmp region
     // A = NAPOT(naturally aligned power-of-two region, 3), support a >=8-byte pmp region
     // When using NAPOT to match a address range [S,S+L), then the pmpaddr_i should be set to (S>>2)|((L>>2)-1)
-    let calc_pmpaddr = |start_addr: usize, length: usize| {
-        (start_addr >> 2) | ((length >> 2) - 1) 
-    };
+    let calc_pmpaddr = |start_addr: usize, length: usize| (start_addr >> 2) | ((length >> 2) - 1);
     let mut pmpcfg0: usize = 0;
     // pmp region 0: RW, A=NAPOT, address range {0x1000_1000, 0x1000}, VIRT_VIRTIO
     //                            address range {0x1000_0000, 0x100}, VIRT_UART0
     //                            aligned address range {0x1000_0000, 0x2000}
-    pmpcfg0 |= 0b11011; 
+    pmpcfg0 |= 0b11011;
     let pmpaddr0 = calc_pmpaddr(0x1000_0000, 0x2000);
-    // pmp region 1: RW, A=NAPOT, address range {0x200_0000, 0x1_0000}, VIRT_CLINT 
+    // pmp region 1: RW, A=NAPOT, address range {0x200_0000, 0x1_0000}, VIRT_CLINT
     pmpcfg0 |= 0b11011 << 8;
     let pmpaddr1 = calc_pmpaddr(0x200_0000, 0x1_0000);
     // pmp region 2: RW, A=NAPOT, address range {0xC00_0000, 0x40_0000}, VIRT_PLIC
@@ -211,7 +209,7 @@ fn set_pmp() {
              in(reg) pmpaddr1,
              in(reg) pmpaddr2,
              in(reg) pmpaddr3,
-        ); 
+        );
     }
 }
 

rustsbi-qemu/src/prv_mem.rs

@@ -11,7 +11,11 @@
 use core::arch::asm;
 use core::mem::{self, MaybeUninit};
 
-use riscv::register::{mcause::{Exception, Mcause, Trap}, mcause, mstatus, mtvec::{self, Mtvec, TrapMode}};
+use riscv::register::{
+    mcause::{self, Exception, Mcause, Trap},
+    mstatus,
+    mtvec::{self, Mtvec, TrapMode},
+};
 
 /// Pointer at supervisor level
 ///
@@ -44,20 +48,22 @@ pub unsafe fn try_read<T>(src: SupervisorPointer<T>) -> Result<T, mcause::Except
         panic!("rustsbi-qemu: mprv should be cleared before try_read")
     }
     for idx in (0..mem::size_of::<T>()).step_by(mem::size_of::<u32>()) {
-        let nr = with_detect_trap(0, || asm!(
-        "li     {mprv_bit}, (1 << 17)",
-        "csrs   mstatus, {mprv_bit}",
-        "lw     {word}, 0({in_s_addr})",
-        "csrc   mstatus, {mprv_bit}",
-        "sw     {word}, 0({out_m_addr})",
-        mprv_bit = out(reg) _,
-        word = out(reg) _,
-        in_s_addr = in(reg) src.inner.cast::<u8>().add(idx),
-        out_m_addr = in(reg) ans.as_mut_ptr().cast::<u8>().add(idx),
-        options(nostack),
-        ));
+        let nr = with_detect_trap(0, || {
+            asm!(
+            "li     {mprv_bit}, (1 << 17)",
+            "csrs   mstatus, {mprv_bit}",
+            "lw     {word}, 0({in_s_addr})",
+            "csrc   mstatus, {mprv_bit}",
+            "sw     {word}, 0({out_m_addr})",
+            mprv_bit = out(reg) _,
+            word = out(reg) _,
+            in_s_addr = in(reg) src.inner.cast::<u8>().add(idx),
+            out_m_addr = in(reg) ans.as_mut_ptr().cast::<u8>().add(idx),
+            options(nostack),
+            )
+        });
         if nr != 0 {
-            return Err(Exception::from(nr))
+            return Err(Exception::from(nr));
         }
     }
     Ok(ans.assume_init())

rustsbi-qemu/src/qemu_pmu.rs

@@ -0,0 +1 @@
+

test-kernel/src/main.rs

@@ -7,8 +7,12 @@
 use core::arch::asm;
 use core::panic::PanicInfo;
 
-use riscv::register::{scause::{self, Exception, Trap}, sepc, /*sie, sstatus, */stvec::{self, TrapMode}};
 use riscv::register::scause::Interrupt;
+use riscv::register::{
+    scause::{self, Exception, Trap},
+    sepc,
+    /*sie, sstatus, */ stvec::{self, TrapMode},
+};
 
 #[macro_use]
 mod console;
@@ -123,9 +127,12 @@ fn test_base_extension() {
         sbi::shutdown()
     }
     println!("<< Test-kernel: Base extension version: {:x}", base_version);
+    let spec_version = sbi::get_spec_version();
+    let major = (spec_version >> 24) & 0x7F;
+    let minor = spec_version & 0xFFFFFF;
     println!(
-        "<< Test-kernel: SBI specification version: {:x}",
-        sbi::get_spec_version()
+        "<< Test-kernel: SBI specification version: {}.{}",
+        major, minor
     );
     println!(
         "<< Test-kernel: SBI implementation Id: {:x}",
@@ -322,4 +329,4 @@ struct TrapFrame {
     a6: usize,
     a7: usize,
     tp: usize,
-}
+}

xtask/src/main.rs

@@ -7,7 +7,6 @@ use std::{
     process::{self, Command, Stdio},
 };
 
-
 // 不要修改DEFAULT_TARGET；如果你需要编译到别的目标，请使用--target编译选项！
 const DEFAULT_TARGET: &'static str = "riscv64imac-unknown-none-elf";
 
@@ -255,7 +254,8 @@ fn xtask_gdb(xtask_env: &XtaskEnv) {
 
     ctrlc::set_handler(move || {
         // when ctrl-c, don't exit gdb
-    }).expect("disable Ctrl-C exit");
+    })
+    .expect("disable Ctrl-C exit");
 
     let status = command.status().expect("run program");
     if !status.success() {