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libretro.cpp
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#include <stdarg.h>
#include "mednafen/git.h"
#include "mednafen/mempatcher.h"
#include "mednafen/git.h"
#include "mednafen/general.h"
#include <compat/msvc.h>
#ifdef NEED_DEINTERLACER
#include "mednafen/video/Deinterlacer.h"
#endif
#include "libretro.h"
#include <rthreads/rthreads.h>
#include <string/stdstring.h>
#include "libretro_cbs.h"
#include "libretro_core_options.h"
#include "libretro_settings.h"
#include "input.h"
#include "disc.h"
#include "mednafen/settings.h"
#include "mednafen/cdrom/cdromif.h"
#include "mednafen/FileStream.h"
#include "mednafen/hash/sha256.h"
#include "mednafen/hash/md5.h"
#include "mednafen/ss/ss.h"
/* Forward declarations */
void MDFN_LoadGameCheats(void *override_ptr);
void MDFN_FlushGameCheats(int nosave);
static INLINE bool DBG_NeedCPUHooks(void) { return false; } // <-- replaces debug.inc
#include <ctype.h>
#include <time.h>
#include <bitset>
struct retro_perf_callback perf_cb;
retro_get_cpu_features_t perf_get_cpu_features_cb = NULL;
retro_log_printf_t log_cb;
static retro_audio_sample_t audio_cb;
static retro_audio_sample_batch_t audio_batch_cb;
static retro_input_poll_t input_poll_cb;
static retro_input_state_t input_state_cb;
static retro_environment_t environ_cb;
void MDFN_DispMessage(const char *format, ...)
{
va_list ap;
struct retro_message msg;
const char *strc = NULL;
char *str = (char*)malloc(4096 * sizeof(char));
va_start(ap,format);
vsnprintf(str, 4096, format, ap);
va_end(ap);
strc = str;
msg.frames = 180;
msg.msg = strc;
environ_cb(RETRO_ENVIRONMENT_SET_MESSAGE, &msg);
free(str);
}
#define MEDNAFEN_CORE_NAME "Beetle Saturn"
#define MEDNAFEN_CORE_VERSION "v1.22.2"
#define MEDNAFEN_CORE_VERSION_NUMERIC 0x00102202
#define MEDNAFEN_CORE_EXTENSIONS "cue|ccd|chd|toc|m3u"
#define MEDNAFEN_CORE_TIMING_FPS 59.82
#define MEDNAFEN_CORE_GEOMETRY_BASE_W 320
#define MEDNAFEN_CORE_GEOMETRY_BASE_H 240
#define MEDNAFEN_CORE_GEOMETRY_MAX_W 704
#define MEDNAFEN_CORE_GEOMETRY_MAX_H 576
#define MEDNAFEN_CORE_GEOMETRY_ASPECT_RATIO (4.0 / 3.0)
#define FB_WIDTH MEDNAFEN_CORE_GEOMETRY_MAX_W
static unsigned frame_count = 0;
static unsigned internal_frame_count = 0;
static bool failed_init = false;
static unsigned image_offset = 0;
static unsigned image_crop = 0;
static unsigned h_mask = 0;
static unsigned first_sl = 0;
static unsigned last_sl = 239;
static unsigned first_sl_pal = 0;
static unsigned last_sl_pal = 287;
static bool is_pal = false;
// Sets how often (in number of output frames/retro_run invocations)
// the internal framerace counter should be updated if
// display_internal_framerate is true.
#define INTERNAL_FPS_SAMPLE_PERIOD 32
static char retro_cd_base_directory[4096];
static char retro_cd_path[4096];
extern "C" char retro_cd_base_name[4096];
extern "C" char retro_save_directory[4096];
extern "C" char retro_base_directory[4096];
#ifdef _WIN32
static char retro_slash = '\\';
#else
static char retro_slash = '/';
#endif
static bool libretro_supports_bitmasks = false;
extern MDFNGI EmulatedSS;
MDFNGI *MDFNGameInfo = NULL;
#include "../MemoryStream.h"
#include "mednafen/ss/ss.h"
#include "mednafen/ss/sound.h"
#include "mednafen/ss/scsp.h"
#include "mednafen/ss/smpc.h"
#include "mednafen/ss/cdb.h"
#include "mednafen/ss/vdp1.h"
#include "mednafen/ss/vdp2.h"
#include "mednafen/ss/scu.h"
#include "mednafen/ss/cart.h"
#include "mednafen/ss/db.h"
static sscpu_timestamp_t MidSync(const sscpu_timestamp_t timestamp);
#ifdef MDFN_SS_DEV_BUILD
uint32 ss_dbg_mask;
#endif
static bool NeedEmuICache;
static const uint8 BRAM_Init_Data[0x10] = { 0x42, 0x61, 0x63, 0x6b, 0x55, 0x70, 0x52, 0x61, 0x6d, 0x20, 0x46, 0x6f, 0x72, 0x6d, 0x61, 0x74 };
static void SaveBackupRAM(void);
static void LoadBackupRAM(void);
static void SaveCartNV(void);
static void LoadCartNV(void);
static void SaveRTC(void);
static void LoadRTC(void);
static MDFN_COLD void BackupBackupRAM(void);
static MDFN_COLD void BackupCartNV(void);
#include "mednafen/ss/sh7095.h"
static uint8 SCU_MSH2VectorFetch(void);
static uint8 SCU_SSH2VectorFetch(void);
static void CheckEventsByMemTS(void);
SH7095 CPU[2]{ {"SH2-M", SS_EVENT_SH2_M_DMA, SCU_MSH2VectorFetch}, {"SH2-S", SS_EVENT_SH2_S_DMA, SCU_SSH2VectorFetch}};
static uint16 BIOSROM[524288 / sizeof(uint16)];
#define WORKRAM_BANK_SIZE_BYTES (1024*1024)
static uint8 WorkRAM[2*WORKRAM_BANK_SIZE_BYTES]; // unified 2MB work ram for linear access.
// Effectively 32-bit in reality, but 16-bit here because of CPU interpreter design(regarding fastmap).
static uint16* WorkRAML = (uint16*)(WorkRAM + (WORKRAM_BANK_SIZE_BYTES*0));
static uint16* WorkRAMH = (uint16*)(WorkRAM + (WORKRAM_BANK_SIZE_BYTES*1));
static uint8 BackupRAM[32768];
static bool BackupRAM_Dirty;
static int64 BackupRAM_SaveDelay;
static int64 CartNV_SaveDelay;
#define SH7095_EXT_MAP_GRAN_BITS 16
static uintptr_t SH7095_FastMap[1U << (32 - SH7095_EXT_MAP_GRAN_BITS)];
int32 SH7095_mem_timestamp;
uint32 SH7095_BusLock;
static uint32 SH7095_DB;
#include "mednafen/ss/scu.inc"
#ifdef HAVE_DEBUG
#include "mednafen/ss/debug.inc"
#endif
static sha256_digest BIOS_SHA256; // SHA-256 hash of the currently-loaded BIOS; used for save state sanity checks.
static std::bitset<1U << (27 - SH7095_EXT_MAP_GRAN_BITS)> FMIsWriteable;
template<typename T>
static void INLINE SH7095_BusWrite(uint32 A, T V, const bool BurstHax, int32* SH2DMAHax);
template<typename T>
static T INLINE SH7095_BusRead(uint32 A, const bool BurstHax, int32* SH2DMAHax);
/*
SH-2 external bus address map:
CS0: 0x00000000...0x01FFFFFF (16-bit)
0x00000000...0x000FFFFF: BIOS ROM (R)
0x00100000...0x0017FFFF: SMPC (R/W; 8-bit mapped as 16-bit)
0x00180000...0x001FFFFF: Backup RAM(32KiB) (R/W; 8-bit mapped as 16-bit)
0x00200000...0x003FFFFF: Low RAM(1MiB) (R/W)
0x01000000...0x017FFFFF: Slave FRT Input Capture Trigger (W)
0x01800000...0x01FFFFFF: Master FRT Input Capture Trigger (W)
CS1: 0x02000000...0x03FFFFFF (SCU managed)
0x02000000...0x03FFFFFF: A-bus CS0 (R/W)
CS2: 0x04000000...0x05FFFFFF (SCU managed)
0x04000000...0x04FFFFFF: A-bus CS1 (R/W)
0x05000000...0x057FFFFF: A-bus Dummy
0x05800000...0x058FFFFF: A-bus CS2 (R/W)
0x05A00000...0x05AFFFFF: SCSP RAM (R/W)
0x05B00000...0x05BFFFFF: SCSP Registers (R/W)
0x05C00000...0x05C7FFFF: VDP1 VRAM (R/W)
0x05C80000...0x05CFFFFF: VDP1 FB RAM (R/W; swappable between two framebuffers, but may be temporarily unreadable at swap time)
0x05D00000...0x05D7FFFF: VDP1 Registers (R/W)
0x05E00000...0x05EFFFFF: VDP2 VRAM (R/W)
0x05F00000...0x05F7FFFF: VDP2 CRAM (R/W; 8-bit writes are illegal)
0x05F80000...0x05FBFFFF: VDP2 Registers (R/W; 8-bit writes are illegal)
0x05FE0000...0x05FEFFFF: SCU Registers (R/W)
0x05FF0000...0x05FFFFFF: SCU Debug/Test Registers (R/W)
CS3: 0x06000000...0x07FFFFFF
0x06000000...0x07FFFFFF: High RAM/SDRAM(1MiB) (R/W)
*/
//
// Never add anything to SH7095_mem_timestamp when DMAHax is true.
//
// When BurstHax is true and we're accessing high work RAM, don't add anything.
//
template<typename T, bool IsWrite>
static INLINE void BusRW_DB_CS0(const uint32 A, uint32& DB, const bool BurstHax, int32* SH2DMAHax)
{
//
// Low(and kinda slow) work RAM
//
if(A >= 0x00200000 && A <= 0x003FFFFF)
{
if(IsWrite)
ne16_wbo_be<T>(WorkRAML, A & 0xFFFFF, DB >> (((A & 1) ^ (2 - sizeof(T))) << 3));
else
DB = (DB & 0xFFFF0000) | ne16_rbo_be<uint16>(WorkRAML, A & 0xFFFFE);
if(!SH2DMAHax)
SH7095_mem_timestamp += 7;
else
*SH2DMAHax -= 7;
return;
}
//
// BIOS ROM
//
if(A >= 0x00000000 && A <= 0x000FFFFF)
{
if(!SH2DMAHax)
SH7095_mem_timestamp += 8;
else
*SH2DMAHax -= 8;
if(!IsWrite)
DB = (DB & 0xFFFF0000) | ne16_rbo_be<uint16>(BIOSROM, A & 0x7FFFE);
return;
}
//
// SMPC
//
if(A >= 0x00100000 && A <= 0x0017FFFF)
{
const uint32 SMPC_A = (A & 0x7F) >> 1;
if(!SH2DMAHax)
{
// SH7095_mem_timestamp += 2;
CheckEventsByMemTS();
}
if(IsWrite)
{
if(sizeof(T) == 2 || (A & 1))
SMPC_Write(SH7095_mem_timestamp, SMPC_A, DB);
}
else
DB = (DB & 0xFFFF0000) | 0xFF00 | SMPC_Read(SH7095_mem_timestamp, SMPC_A);
return;
}
//
// Backup RAM
//
if(A >= 0x00180000 && A <= 0x001FFFFF)
{
if(!SH2DMAHax)
SH7095_mem_timestamp += 8;
else
*SH2DMAHax -= 8;
if(IsWrite)
{
if(sizeof(T) != 1 || (A & 1))
{
BackupRAM[(A >> 1) & 0x7FFF] = DB;
BackupRAM_Dirty = true;
}
}
else
DB = (DB & 0xFFFF0000) | 0xFF00 | BackupRAM[(A >> 1) & 0x7FFF];
return;
}
//
// FRT trigger region
//
if(A >= 0x01000000 && A <= 0x01FFFFFF)
{
if(!SH2DMAHax)
SH7095_mem_timestamp += 8;
else
*SH2DMAHax -= 8;
//printf("FT FRT%08x %zu %08x %04x %d %d\n", A, sizeof(T), A, V, SMPC_IsSlaveOn(), SH7095_mem_timestamp);
if(IsWrite)
{
if(sizeof(T) != 1)
{
const unsigned c = ((A >> 23) & 1) ^ 1;
if(!c || SMPC_IsSlaveOn())
{
CPU[c].SetFTI(true);
CPU[c].SetFTI(false);
}
}
}
return;
}
//
//
//
if(!SH2DMAHax)
SH7095_mem_timestamp += 4;
else
*SH2DMAHax -= 4;
if(IsWrite)
SS_DBG(SS_DBG_WARNING, "[SH2 BUS] Unknown %zu-byte write of 0x%08x to 0x%08x\n", sizeof(T), DB >> (((A & 1) ^ (2 - sizeof(T))) << 3), A);
else
SS_DBG(SS_DBG_WARNING, "[SH2 BUS] Unknown %zu-byte read from 0x%08x\n", sizeof(T), A);
}
template<typename T, bool IsWrite>
static INLINE void BusRW_DB_CS123(const uint32 A, uint32& DB, const bool BurstHax, int32* SH2DMAHax)
{
//
// CS3: High work RAM/SDRAM, 0x06000000 ... 0x07FFFFFF
//
if(A >= 0x06000000)
{
if(!IsWrite || sizeof(T) == 4)
ne16_rwbo_be<uint32, IsWrite>(WorkRAMH, A & 0xFFFFC, &DB);
else
ne16_wbo_be<T>(WorkRAMH, A & 0xFFFFF, DB >> (((A & 3) ^ (4 - sizeof(T))) << 3));
if(!BurstHax)
{
if(!SH2DMAHax)
{
if(IsWrite)
{
SH7095_mem_timestamp = (SH7095_mem_timestamp + 4) &~ 3;
}
else
{
SH7095_mem_timestamp += 7;
}
}
else
*SH2DMAHax -= IsWrite ? 3 : 6;
}
return;
}
//
// CS1 and CS2: SCU
//
if(!IsWrite)
DB = 0;
SCU_FromSH2_BusRW_DB<T, IsWrite>(A, &DB, SH2DMAHax);
}
template<typename T>
static void INLINE SH7095_BusWrite(uint32 A, T V, const bool BurstHax, int32* SH2DMAHax)
{
uint32 DB = SH7095_DB;
if(A < 0x02000000) // CS0, configured as 16-bit
{
if(sizeof(T) == 4)
{
// TODO/FIXME: Don't allow DMA transfers to occur between the two 16-bit accesses.
//if(!SH2DMAHax)
// SH7095_BusLock++;
DB = (DB & 0xFFFF0000) | (V >> 16);
BusRW_DB_CS0<uint16, true>(A, DB, BurstHax, SH2DMAHax);
DB = (DB & 0xFFFF0000) | (uint16)V;
BusRW_DB_CS0<uint16, true>(A | 2, DB, BurstHax, SH2DMAHax);
//if(!SH2DMAHax)
// SH7095_BusLock--;
}
else
{
const uint32 shift = ((A & 1) ^ (2 - sizeof(T))) << 3;
const uint32 mask = (0xFFFF >> ((2 - sizeof(T)) * 8)) << shift;
DB = (DB & ~mask) | (V << shift);
BusRW_DB_CS0<T, true>(A, DB, BurstHax, SH2DMAHax);
}
}
else // CS1, CS2, CS3; 32-bit
{
const uint32 shift = ((A & 3) ^ (4 - sizeof(T))) << 3;
const uint32 mask = (0xFFFFFFFF >> ((4 - sizeof(T)) * 8)) << shift;
DB = (DB & ~mask) | (V << shift); // //ne32_wbo_be<T>(&DB, A & 0x3, V);
BusRW_DB_CS123<T, true>(A, DB, BurstHax, SH2DMAHax);
}
SH7095_DB = DB;
}
template<typename T>
static T INLINE SH7095_BusRead(uint32 A, const bool BurstHax, int32* SH2DMAHax)
{
uint32 DB = SH7095_DB;
T ret;
if(A < 0x02000000) // CS0, configured as 16-bit
{
if(sizeof(T) == 4)
{
// TODO/FIXME: Don't allow DMA transfers to occur between the two 16-bit accesses.
//if(!SH2DMAHax)
// SH7095_BusLock++;
BusRW_DB_CS0<uint16, false>(A, DB, BurstHax, SH2DMAHax);
ret = DB << 16;
BusRW_DB_CS0<uint16, false>(A | 2, DB, BurstHax, SH2DMAHax);
ret |= (uint16)DB;
//if(!SH2DMAHax)
// SH7095_BusLock--;
}
else
{
BusRW_DB_CS0<T, false>(A, DB, BurstHax, SH2DMAHax);
ret = DB >> (((A & 1) ^ (2 - sizeof(T))) << 3);
}
}
else // CS1, CS2, CS3; 32-bit
{
BusRW_DB_CS123<T, false>(A, DB, BurstHax, SH2DMAHax);
ret = DB >> (((A & 3) ^ (4 - sizeof(T))) << 3);
// SDRAM leaves data bus in a weird state after read...
//if(A >= 0x06000000)
// DB = 0;
}
SH7095_DB = DB;
return ret;
}
//
//
//
static MDFN_COLD uint8 CheatMemRead(uint32 A)
{
A &= (1U << 27) - 1;
return ne16_rbo_be<uint8>(SH7095_FastMap[A >> SH7095_EXT_MAP_GRAN_BITS], A);
}
static MDFN_COLD void CheatMemWrite(uint32 A, uint8 V)
{
A &= (1U << 27) - 1;
if(FMIsWriteable[A >> SH7095_EXT_MAP_GRAN_BITS])
{
ne16_wbo_be<uint8>(SH7095_FastMap[A >> SH7095_EXT_MAP_GRAN_BITS], A, V);
for(unsigned c = 0; c < 2; c++)
{
if(CPU[c].CCR & SH7095::CCR_CE)
{
for(uint32 Abase = 0x00000000; Abase < 0x20000000; Abase += 0x08000000)
{
CPU[c].Write_UpdateCache<uint8>(Abase + A, V);
}
}
}
}
}
//
//
//
static void SetFastMemMap(uint32 Astart, uint32 Aend, uint16* ptr, uint32 length, bool is_writeable)
{
const uint64 Abound = (uint64)Aend + 1;
assert((Astart & ((1U << SH7095_EXT_MAP_GRAN_BITS) - 1)) == 0);
assert((Abound & ((1U << SH7095_EXT_MAP_GRAN_BITS) - 1)) == 0);
assert((length & ((1U << SH7095_EXT_MAP_GRAN_BITS) - 1)) == 0);
assert(length > 0);
assert(length <= (Abound - Astart));
for(uint64 A = Astart; A < Abound; A += (1U << SH7095_EXT_MAP_GRAN_BITS))
{
uintptr_t tmp = (uintptr_t)ptr + ((A - Astart) % length);
if(A < (1U << 27))
FMIsWriteable[A >> SH7095_EXT_MAP_GRAN_BITS] = is_writeable;
SH7095_FastMap[A >> SH7095_EXT_MAP_GRAN_BITS] = tmp - A;
}
}
static uint16 fmap_dummy[(1U << SH7095_EXT_MAP_GRAN_BITS) / sizeof(uint16)];
static MDFN_COLD void InitFastMemMap(void)
{
for(unsigned i = 0; i < sizeof(fmap_dummy) / sizeof(fmap_dummy[0]); i++)
{
fmap_dummy[i] = 0;
}
FMIsWriteable.reset();
MDFNMP_Init(1ULL << SH7095_EXT_MAP_GRAN_BITS, (1ULL << 27) / (1ULL << SH7095_EXT_MAP_GRAN_BITS));
for(uint64 A = 0; A < 1ULL << 32; A += (1U << SH7095_EXT_MAP_GRAN_BITS))
{
SH7095_FastMap[A >> SH7095_EXT_MAP_GRAN_BITS] = (uintptr_t)fmap_dummy - A;
}
}
void SS_SetPhysMemMap(uint32 Astart, uint32 Aend, uint16* ptr, uint32 length, bool is_writeable)
{
assert(Astart < 0x20000000);
assert(Aend < 0x20000000);
if(!ptr)
{
ptr = fmap_dummy;
length = sizeof(fmap_dummy);
}
for(uint32 Abase = 0; Abase < 0x40000000; Abase += 0x20000000)
SetFastMemMap(Astart + Abase, Aend + Abase, ptr, length, is_writeable);
}
#include "mednafen/ss/sh7095.inc"
static bool Running;
event_list_entry events[SS_EVENT__COUNT];
static sscpu_timestamp_t next_event_ts;
template<unsigned c>
static sscpu_timestamp_t SH_DMA_EventHandler(sscpu_timestamp_t et)
{
if(et < SH7095_mem_timestamp)
{
//printf("SH-2 DMA %d reschedule %d->%d\n", c, et, SH7095_mem_timestamp);
return SH7095_mem_timestamp;
}
// Must come after the (et < SH7095_mem_timestamp) check.
if(MDFN_UNLIKELY(SH7095_BusLock))
return et + 1;
return CPU[c].DMA_Update(et);
}
//
//
//
static MDFN_COLD void InitEvents(void)
{
for(unsigned i = 0; i < SS_EVENT__COUNT; i++)
{
if(i == SS_EVENT__SYNFIRST)
events[i].event_time = 0;
else if(i == SS_EVENT__SYNLAST)
events[i].event_time = 0x7FFFFFFF;
else
events[i].event_time = 0; //SS_EVENT_DISABLED_TS;
events[i].prev = (i > 0) ? &events[i - 1] : NULL;
events[i].next = (i < (SS_EVENT__COUNT - 1)) ? &events[i + 1] : NULL;
}
events[SS_EVENT_SH2_M_DMA].event_handler = &SH_DMA_EventHandler<0>;
events[SS_EVENT_SH2_S_DMA].event_handler = &SH_DMA_EventHandler<1>;
events[SS_EVENT_SCU_DMA].event_handler = SCU_UpdateDMA;
events[SS_EVENT_SCU_DSP].event_handler = SCU_UpdateDSP;
events[SS_EVENT_SMPC].event_handler = SMPC_Update;
events[SS_EVENT_VDP1].event_handler = VDP1::Update;
events[SS_EVENT_VDP2].event_handler = VDP2::Update;
events[SS_EVENT_CDB].event_handler = CDB_Update;
events[SS_EVENT_SOUND].event_handler = SOUND_Update;
events[SS_EVENT_CART].event_handler = CART_GetEventHandler();
events[SS_EVENT_MIDSYNC].event_handler = MidSync;
events[SS_EVENT_MIDSYNC].event_time = SS_EVENT_DISABLED_TS;
}
static void RebaseTS(const sscpu_timestamp_t timestamp)
{
for(unsigned i = 0; i < SS_EVENT__COUNT; i++)
{
if(i == SS_EVENT__SYNFIRST || i == SS_EVENT__SYNLAST)
continue;
assert(events[i].event_time > timestamp);
if(events[i].event_time != SS_EVENT_DISABLED_TS)
events[i].event_time -= timestamp;
}
next_event_ts = events[SS_EVENT__SYNFIRST].next->event_time;
}
void SS_SetEventNT(event_list_entry* e, const sscpu_timestamp_t next_timestamp)
{
if(next_timestamp < e->event_time)
{
event_list_entry *fe = e;
do
{
fe = fe->prev;
} while(next_timestamp < fe->event_time);
// Remove this event from the list, temporarily of course.
e->prev->next = e->next;
e->next->prev = e->prev;
// Insert into the list, just after "fe".
e->prev = fe;
e->next = fe->next;
fe->next->prev = e;
fe->next = e;
e->event_time = next_timestamp;
}
else if(next_timestamp > e->event_time)
{
event_list_entry *fe = e;
do
{
fe = fe->next;
} while(next_timestamp > fe->event_time);
// Remove this event from the list, temporarily of course
e->prev->next = e->next;
e->next->prev = e->prev;
// Insert into the list, just BEFORE "fe".
e->prev = fe->prev;
e->next = fe;
fe->prev->next = e;
fe->prev = e;
e->event_time = next_timestamp;
}
next_event_ts = (Running ? events[SS_EVENT__SYNFIRST].next->event_time : 0);
}
// Called from debug.cpp too.
void ForceEventUpdates(const sscpu_timestamp_t timestamp)
{
CPU[0].ForceInternalEventUpdates();
if(SMPC_IsSlaveOn())
CPU[1].ForceInternalEventUpdates();
for(unsigned evnum = SS_EVENT__SYNFIRST + 1; evnum < SS_EVENT__SYNLAST; evnum++)
{
if(events[evnum].event_time != SS_EVENT_DISABLED_TS)
SS_SetEventNT(&events[evnum], events[evnum].event_handler(timestamp));
}
next_event_ts = (Running ? events[SS_EVENT__SYNFIRST].next->event_time : 0);
}
static INLINE bool EventHandler(const sscpu_timestamp_t timestamp)
{
event_list_entry *e = NULL;
while(timestamp >= (e = events[SS_EVENT__SYNFIRST].next)->event_time) // If Running = 0, EventHandler() may be called even if there isn't an event per-se, so while() instead of do { ... } while
{
#ifdef MDFN_SS_DEV_BUILD
const sscpu_timestamp_t etime = e->event_time;
#endif
sscpu_timestamp_t nt;
nt = e->event_handler(e->event_time);
#ifdef MDFN_SS_DEV_BUILD
if(MDFN_UNLIKELY(nt <= etime))
{
fprintf(stderr, "which=%d event_time=%d nt=%d timestamp=%d\n", (int)(e - events), etime, nt, timestamp);
assert(nt > etime);
}
#endif
SS_SetEventNT(e, nt);
}
return(Running);
}
static void CheckEventsByMemTS_Sub(void)
{
EventHandler(SH7095_mem_timestamp);
}
static void CheckEventsByMemTS(void)
{
if(MDFN_UNLIKELY(SH7095_mem_timestamp >= next_event_ts))
{
//puts("Woot");
CheckEventsByMemTS_Sub();
}
}
void SS_RequestMLExit(void)
{
Running = 0;
next_event_ts = 0;
}
#pragma GCC push_options
#if !defined(__clang__) && defined(__GNUC__) && __GNUC__ < 5
// gcc 5.3.0 and 6.1.0 produce some braindead code for the big switch() statement at -Os.
#pragma GCC optimize("Os,no-unroll-loops,no-peel-loops,no-crossjumping")
#else
#pragma GCC optimize("O2,no-unroll-loops,no-peel-loops,no-crossjumping")
#endif
template<bool EmulateICache, bool DebugMode>
static int32 NO_INLINE RunLoop(EmulateSpecStruct* espec)
{
sscpu_timestamp_t eff_ts = 0;
//printf("%d %d\n", SH7095_mem_timestamp, CPU[0].timestamp);
do
{
do
{
#ifdef HAVE_DEBUG
if(DebugMode)
DBG_CPUHandler<0>(eff_ts);
#endif
CPU[0].Step<0, EmulateICache, DebugMode>();
CPU[0].DMA_BusTimingKludge();
while(MDFN_LIKELY(CPU[0].timestamp > CPU[1].timestamp))
{
#ifdef HAVE_DEBUG
if(DebugMode)
DBG_CPUHandler<1>(eff_ts);
#endif
CPU[1].Step<1, EmulateICache, DebugMode>();
}
eff_ts = CPU[0].timestamp;
if(SH7095_mem_timestamp > eff_ts)
eff_ts = SH7095_mem_timestamp;
else
SH7095_mem_timestamp = eff_ts;
} while(MDFN_LIKELY(eff_ts < next_event_ts));
} while(MDFN_LIKELY(EventHandler(eff_ts)));
//printf(" End: %d %d -- %d\n", SH7095_mem_timestamp, CPU[0].timestamp, eff_ts);
return eff_ts;
}
#pragma GCC pop_options
// Must not be called within an event or read/write handler.
void SS_Reset(bool powering_up)
{
SH7095_BusLock = 0;
if(powering_up)
{
memset(WorkRAM, 0x00, sizeof(WorkRAM)); // TODO: Check real hardware
}
if(powering_up)
{
CPU[0].TruePowerOn();
CPU[1].TruePowerOn();
}
SCU_Reset(powering_up);
CPU[0].Reset(powering_up);
SMPC_Reset(powering_up);
VDP1::Reset(powering_up);
VDP2::Reset(powering_up);
CDB_Reset(powering_up);
SOUND_Reset(powering_up);
CART_Reset(powering_up);
}
static EmulateSpecStruct* espec;
static bool AllowMidSync;
static int32 cur_clock_div;
static int64 UpdateInputLastBigTS;
static INLINE void UpdateSMPCInput(const sscpu_timestamp_t timestamp)
{
SMPC_TransformInput();
int32 elapsed_time = (((int64)timestamp * cur_clock_div * 1000 * 1000) - UpdateInputLastBigTS) / (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1));
UpdateInputLastBigTS += (int64)elapsed_time * (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1));
SMPC_UpdateInput(elapsed_time);
}
static sscpu_timestamp_t MidSync(const sscpu_timestamp_t timestamp)
{
if(AllowMidSync)
{
//
// Don't call SOUND_Update() here, it's not necessary and will subtly alter emulation behavior from the perspective of the emulated program
// (which is not a problem in and of itself, but it's preferable to keep settings from altering emulation behavior when they don't need to).
//
//printf("MidSync: %d\n", VDP2::PeekLine());
//{
// espec->SoundBufSize += SOUND_FlushOutput();
// espec->MasterCycles = timestamp * cur_clock_div;
//}
//printf("%d\n", espec->SoundBufSize);
SMPC_UpdateOutput();
input_poll_cb();
input_update(libretro_supports_bitmasks, input_state_cb );
UpdateSMPCInput(timestamp);
AllowMidSync = false;
}
return SS_EVENT_DISABLED_TS;
}
static void Emulate(EmulateSpecStruct* espec_arg)
{
int32 end_ts;
espec = espec_arg;
AllowMidSync = setting_midsync;
cur_clock_div = SMPC_StartFrame(espec);
UpdateSMPCInput(0);
VDP2::StartFrame(espec, cur_clock_div == 61);
CART_SetCPUClock(EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1), cur_clock_div);
espec->SoundBufSize = 0;
espec->MasterCycles = 0;
espec->soundmultiplier = 1;
//
//
//
Running = true; // Set before ForceEventUpdates()
ForceEventUpdates(0);
#ifdef WANT_DEBUGGER
#define RLTDAT true
#else
#define RLTDAT false
#endif
static int32 (*const rltab[2][2])(EmulateSpecStruct*) =
{
// DebugMode=false DebugMode=true
{ RunLoop<false, false>, RunLoop<false, RLTDAT> }, // EmulateICache=false
{ RunLoop<true, false>, RunLoop<true, RLTDAT> }, // EmulateICache=true
};
#undef RLTDAT
end_ts = rltab[NeedEmuICache][DBG_NeedCPUHooks()](espec);
ForceEventUpdates(end_ts);
//
SMPC_EndFrame(espec, end_ts);
//
//
//
RebaseTS(end_ts);
CDB_ResetTS();
SOUND_ResetTS();
VDP1::AdjustTS(-end_ts);
VDP2::AdjustTS(-end_ts);
SMPC_ResetTS();
SCU_AdjustTS(-end_ts);
CART_AdjustTS(-end_ts);
UpdateInputLastBigTS -= (int64)end_ts * cur_clock_div * 1000 * 1000;
if(!(SH7095_mem_timestamp & 0x40000000)) // or maybe >= 0 instead?
SH7095_mem_timestamp -= end_ts;
CPU[0].AdjustTS(-end_ts);
if(SMPC_IsSlaveOn())
CPU[1].AdjustTS(-end_ts);
//
//
//
espec->MasterCycles = end_ts * cur_clock_div;
espec->SoundBufSize += SOUND_FlushOutput();
espec->NeedSoundReverse = false;
SMPC_UpdateOutput();
//
//
//
if(BackupRAM_Dirty)
{
BackupRAM_SaveDelay = (int64)3 * (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1)); // 3 second delay
BackupRAM_Dirty = false;
}
else if(BackupRAM_SaveDelay > 0)
{
BackupRAM_SaveDelay -= espec->MasterCycles;
if(BackupRAM_SaveDelay <= 0)
{
try
{
SaveBackupRAM();
}
catch(std::exception& e)
{
MDFN_DispMessage("%s", e.what());
BackupRAM_SaveDelay = (int64)60 * (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1)); // 60 second retry delay.
}
}
}
if(CART_GetClearNVDirty())
CartNV_SaveDelay = (int64)3 * (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1)); // 3 second delay
else if(CartNV_SaveDelay > 0)
{
CartNV_SaveDelay -= espec->MasterCycles;
if(CartNV_SaveDelay <= 0)
{
try
{
SaveCartNV();
}
catch(std::exception& e)
{
MDFN_DispMessage("%s", e.what());
CartNV_SaveDelay = (int64)60 * (EmulatedSS.MasterClock / MDFN_MASTERCLOCK_FIXED(1)); // 60 second retry delay.
}
}
}
}
//
//
//
static MDFN_COLD void Cleanup(void)
{
CART_Kill();
#ifdef HAVE_DEBUG
DBG_Kill();