This project demonstrates the implementation of an Automatic Washing Machine controller using Verilog Hardware Description Language (HDL). The controller is designed using a Finite-State Machine (FSM) model and simulated using MODELSIM software.
For detailed information about the project, including specifications, block diagram, FSM diagram, Verilog code, test bench, waveform, and simulation results, please refer to the project report:
The Automatic Washing Machine controller is designed to control the various functionalities of a washing machine. It operates within distinct states, including Check_Door, Fill_Water, Add_Detergent, Drain_Water, and Spin. The controller consists of two main blocks: a Finite-State Machine (FSM) block and a Timer block.
This project demonstrates the practical application of Verilog HDL in the development of an Automatic Washing Machine controller. By implementing the controller using an FSM model, we have showcased the versatility of Verilog HDL in designing complex control systems.
For more details, please refer to the project report.