GitHub - salilkanitkar/cache_simulator: Course Project: Flexible Cache and Memory hierarchy simulator.

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Name		Name	Last commit message	Last commit date
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debug_runs		debug_runs
traces		traces
validation_runs		validation_runs
Graph6.xlsx		Graph6.xlsx
Makefile		Makefile
README		README
gnuplot_cmds		gnuplot_cmds
graph1.sh		graph1.sh
graph2.sh		graph2.sh
graph3.sh		graph3.sh
graph4.sh		graph4.sh
graph5.sh		graph5.sh
graph6.sh		graph6.sh
main.c		main.c
main.h		main.h
report.pdf		report.pdf
run_debug_runs.sh		run_debug_runs.sh
run_valiation_runs.sh		run_valiation_runs.sh
runme.sh		runme.sh
utils.c		utils.c

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Implementation of flexible cache and memory hierarchy simulator.

Problem Definition:
Design a generic cache module that can be used at any level in a memory hierarchy. 
So it can instantiated as L1 cache, L2 cache etc.
Cache should be configurable in terms of supporting any cache size, associativity and block size.

Specification of Simulator:
The simulator must accept 10 command line arguments as shown below - 
sim_cache <BLOCKSIZE> 
          <L1_SIZE> <L1_ASSOC> <L1_PREF_N> <L1_PREF_M>
	  <L2_Size> <L2_ASSOC> <L2_PREF_N> <L2_PREF_M>
	  <trace_file>

AUthor: Salil Kanitkar (sskanitk@ncsu.edu)