UART_HUB

UART hub project for the Tiny-FPGA-B-Series See: http://tinyfpga.com/b-series-guide.html https://github.com/tinyfpga/TinyFPGA-B-Series

This project contains some simple building block modules for creating a simple UART interface on an FPGA using verilog.

The project currently WORKS. However, there is some issue on the UART_TX and UART_RX modules that requires a latch. This latch causes the sythesis to state the design is not guarenteed to work at any clock freq. The project does, however, work at 16MHz on the B2 board.

uart.v

uart_tx

Parameters

CLOCK_FREQ

Default=16000000 (16MHz)

The input clock frequency. Used to generate the selected baud rate.

BAUD

Default=9600

Sets the UART baud rate.

START_BITS

Default=1

Start bits are the low bits at the beginning of the data frame and when combined with stop bits guarentee at least one transition to signal a new bit.

STOP_BITS

Default=1

Stop bits are the amount of high bits at the end of the data frame.

PARITY

Default=0

Parity bits are located at the end of the data, before the stop bits. They are a form of checksum. Not currently implemented in any form.

WIDTH

Default=8

Width defines the length of the data to be transmitted. It defines the size of the transmit buffer.

Ports

Inputs

clk

Size=1 bit

Input clock signal. Used as clock for flip-flops and for generating the UART's baud.

new_data

Size=1 bit

This is a strobe that informs the module that data has been written to the input buffer and is ready to be sent. This signal should be high for at least one full clock cycle and must be low before the module is ready to send the next byte to prevent sending a duplicate byte.

char

Size=WIDTH

This is the tranmit input buffer. It is of length WIDTH. It must be set to the correct value before the new_data strobe.

Outputs

rdy

Size=1 bit

This signal is high when the module is ready to recieve new data. This signal also "or"s with the output to make it high when the module is not active.

out_bit

Size=1 bit

This is the serial output (TX) of the module.

uart_rx

Parameters

CLOCK_FREQ

Default=16000000 (16MHz)

This is the modules clock frequency and is used to determine the speed based on the baud of the module.

BAUD

Default=9600

Sets the UART baud rate.

START_BITS

Default=1

Start bits are the low bits at the beginning of the data frame and when combined with stop bits guarentee at least one transition to signal a new bit.

STOP_BITS

Default=1

Stop bits are the amount of high bits at the end of the data frame.

PARITY

Default=0

Parity bits are located at the end of the data, before the stop bits. They are a form of checksum. Not currently implemented in any form.

WIDTH

Default=8

Width defines the length of the data to be transmitted. It defines the size of the transmit buffer.

Ports

Inputs

clk

Size=1 bit

Input clock signal. Used as clock for flip-flops and for generating the UART's baud.

data_in

Size=1 bit

This is the serial data in (RX) for the module.

Outputs

data_out

Size=WIDTH

This is the output register for recieved serial data. This register is undefined until the new_data strobe is high.

new_data

Size=1 bit

This is the output strobe of the module. When it is high, data is ready to be read from the data_out port. This signal is high for one complete clock cycle and is directly compatible with the uart_tx module.

uart_hub.v

This is the top level module. It is a simple uart passthrough module. Pin13 serves as a heartbeat to verify the part is working correctly and is not in bootloader mode. The serial in (RX) is on pin23. Serial out (TX) is on pin22.

uart_hub

Ports

Inputs

pin3_clk_16mhz

This signal comes from the resonator on the B2 board and generates the logic clock.

pin23

This pin is the serial in port (RX) for the passthrough.

Outputs

pin1_usb_dp

Signal not used.

pin2_usb_dn

Signal not used.

pin13

This pin is the heartbeat for the board. It cycles about once every 1s.

pin22

This pin is the serial out port (TX) for the passthrough.