Please add a "dead time" PWM function & PWM frequency halves after power cycle

[nikowot]

Hello Sam,
Thank you for making your library available.
Please add a PWM "dead time" function and define a complementary signal to the library: "TimerFour".

[nikowot]

I have encountered the problem of generating half the frequency at the output as soon as the power is switched on.
After performing a manual RESET, the frequency is correct.

[samverstraete]

Hi @nikowot

Not sure how this could happen. I would check the datasheet of the ATMega and see if there's another peripheral using the same clock source as timer 4.

Otherwise, this code is basically a copy of Paul Stoffregens TimerThree code, maybe you can check there if someone had a similar problem with timer 3...

[nikowot]

Hello, Sam I ran your example program on a blank Leonardo board: /* Name: SlowSawtooth.ino Created: 3/28/2020 10:44:36 PM Author: Sam Verstraete */ #include <TimerFour.h> // the setup function runs once when you press reset or power the board void setup() { Timer4.initialize(100); //10kHz Serial.begin(115200); } // the loop function runs over and over again until power down or reset void loop() { for (int i = 0; i < 1023; i++) { Timer4.pwm(9, i); Serial.println(i); delay(10); } } I got the *5kHz* frequency after power-up and before manual RESET. And the *10kHz* frequency after manual RESET. See attached illustration. I found a description of a similar problem on the web: /"I have programmed the code and registers so that the frequency is changeable from 10kHz to 100kHz. But after power on/off the frequency changes from 5kHz to 50kHz."/ https://stackoverflow.com/questions/54814895/arduino-timer4-custom-pwm-issue I conclude that this is some kind of problem with the microcontroller. I would be grateful if you could analyse this problem and find the solution.

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-- Best Regards Norbert Attention: This email is intended solely for the addressee. Access to this email by anyone else is unauthorised. I do not permit the contents of this correspondence to be analysed or copied by automated computer systems, in particular Alphabet Inc. and its affiliates. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful. Should you receive this message by mistake, you are hereby notified that any disclosure, reproduction, distribution or use of this message is strictly prohibited. Please inform the sender by reply transmission and delete the message without opening the attachments. ***************************************************** W dniu 2023-04-28 o 22:55, Sam Verstraete pisze:

Hi @nikowot <https://github.com/nikowot> Not sure how this could happen. I would check the datasheet of the ATMega and see if there's another peripheral using the same clock source as timer 4. Otherwise, this code is basically a copy of Paul Stoffregens TimerThree <https://github.com/PaulStoffregen/TimerThree> code, maybe you can check there if someone had a similar problem with timer 3... — Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/A5EGHKFK5XKMYEBT5QFKIC3XDQ4G3ANCNFSM6AAAAAAV7O242M>. You are receiving this because you were mentioned.Message ID: ***@***.***>

[samverstraete]

Looks like something changes the PLL config after a power cycle. I've changed to code to force the PLL to the right config (96Mhz) when setPeriod is called (or initialize).
Fixed in release v1.0.1

[nikowot]

Hello, I tested - it works fine after the change! Thank you for your analysis and the changes made. I have the satisfaction of having contributed to the improvement of this library.

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-- Pozdrawiam, Norbert ***************************************************** Attention: I do not permit the contents of this correspondence to be analysed or copied by automated computer systems, in particular Alphabet Inc. and its affiliates. ***************************************************** W dniu 2023-04-29 o 23:00, Sam Verstraete pisze:

Looks like something changes the PLL config after a power cycle. I've changed to code to force the PLL to the right config (96Mhz) when setPeriod is called (or initialize). Fixed in release v1.0.1 — Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/A5EGHKDHFBEAVHYH2J3JJMLXDWFQVANCNFSM6AAAAAAV7O242M>. You are receiving this because you were mentioned.Message ID: ***@***.***>