verilog-workshop

Examples for my Verilog workshop/Lunch and Learn

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
1-hello_world.v		1-hello_world.v
2-variables.v		2-variables.v
3-always.v		3-always.v
4-assignment.v		4-assignment.v
5-assign.v		5-assign.v
6-module.v		6-module.v
7-param.v		7-param.v
8-task.v		8-task.v
9-function.v		9-function.v
Makefile		Makefile
README.md		README.md

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