GitHub - sarpuser/SystemVerilog-Projects: This repo includes all the SystemVerilog projects I have created in my digital design class, along with RTL and state machine diagrams, and simulation results. All simulations were done on Quartus Prime Lite.

This repository has been archived by the owner on Jul 16, 2022. It is now read-only.

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This repo includes all the SystemVerilog projects I have created in my digital design class, along with RTL and state machine diagrams, and simulation results. All simulations were done on Quartus Prime Lite.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU		ALU
Barrel Shifter		Barrel Shifter
Booth Multiplier		Booth Multiplier
Carry Lookahead Adder		Carry Lookahead Adder
Full Adder		Full Adder
Gray Code to Binary Converter		Gray Code to Binary Converter
Integer Multiplier		Integer Multiplier
Johnson Counter		Johnson Counter
LFSR		LFSR
UART Control System		UART Control System
UART		UART
Universal Shift Register		Universal Shift Register
Up:Down Counter		Up:Down Counter
Vending Machine		Vending Machine