Additional changes for SDSoC support

This project is still incomplete and in development. -Changed video input pipeline to use 8-bit grayscale input. This reduces DDR bandwidth used by the input pipeline. This will likey be changed to YUYV (aka YUV422) input with subsampling before launch so that color input is possible. -Changed clock speed of AXI memory interconnect to ~120 MHZ. This allows the design to meet timing, but makes 1080p input or output not possible because the axi stream buses are also currently clocked with this clock. This should probably be changed before launch to support 1080p again (at least on the output). -Added notes to SDSoC staging area describing that Linux support is currently broken. -Remove lib_bsp because you are not supposed to include libxil.a in SDSoC 2016.4 because it will automatically generate a BSP for you. For some reason you still need to include the "include" folder though.
sbobrowicz · Mar 10, 2017 · 55cc502 · 55cc502
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commit 55cc502
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Showing 270 changed files with 498,061 additions and 89,115 deletions.
diff --git a/hw_handoff/Arty_Z7_20_wrapper.hdf b/hw_handoff/Arty_Z7_20_wrapper.hdf
diff --git a/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf b/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf
diff --git a/sdk/displaydemo_bsp/system.mss b/sdk/displaydemo_bsp/system.mss
@@ -288,4 +288,16 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = xadc_wiz_0
 END
 
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_video
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = vtc
+ PARAMETER DRIVER_VER = 7.2
+ PARAMETER HW_INSTANCE = v_tc_1
+END
+
 
diff --git a/sdk/fsbl_bsp/system.mss b/sdk/fsbl_bsp/system.mss
@@ -288,6 +288,18 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = xadc_wiz_0
 END
 
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_video
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = vtc
+ PARAMETER DRIVER_VER = 7.2
+ PARAMETER HW_INSTANCE = v_tc_1
+END
+
 
 BEGIN LIBRARY
  PARAMETER LIBRARY_NAME = xilffs

diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20.bd b/src/bd/Arty_Z7_20/Arty_Z7_20.bd
diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20.bxml b/src/bd/Arty_Z7_20/Arty_Z7_20.bxml
@@ -2,9 +2,9 @@
 <Root MajorVersion="0" MinorVersion="33">
   <CompositeFile CompositeFileTopName="Arty_Z7_20" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1488218731"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1488218731"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1488218731"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1488829463"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1488829463"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1488829463"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="ip\Arty_Z7_20_axi_dynclk_0_0\Arty_Z7_20_axi_dynclk_0_0.xci" Type="IP">
         <Instance HierarchyPath="axi_dynclk_0"/>
@@ -212,6 +212,70 @@
         <UsedIn Val="IMPLEMENTATION"/>
         <UsedIn Val="SIMULATION"/>
       </File>
+      <File Name="ip\Arty_Z7_20_dvi2rgb_0_0\Arty_Z7_20_dvi2rgb_0_0.xci" Type="IP">
+        <Instance HierarchyPath="dvi2rgb_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_v_vid_in_axi4s_0_0\Arty_Z7_20_v_vid_in_axi4s_0_0.xci" Type="IP">
+        <Instance HierarchyPath="v_vid_in_axi4s_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_proc_sys_reset_0_3\Arty_Z7_20_proc_sys_reset_0_3.xci" Type="IP">
+        <Instance HierarchyPath="proc_sys_reset_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_v_tc_1_0\Arty_Z7_20_v_tc_1_0.xci" Type="IP">
+        <Instance HierarchyPath="v_tc_1"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_xbar_1\Arty_Z7_20_xbar_1.xci" Type="IP">
+        <Instance HierarchyPath="axi_mem_intercon/xbar"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_axi_gpio_0_0\Arty_Z7_20_axi_gpio_0_0.xci" Type="IP">
+        <Instance HierarchyPath="axi_gpio_video"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_axis_subset_converter_0_1\Arty_Z7_20_axis_subset_converter_0_1.xci" Type="IP">
+        <Instance HierarchyPath="axis_subset_converter_1"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
+      <File Name="ip\Arty_Z7_20_v_rgb2ycrcb_0_0\Arty_Z7_20_v_rgb2ycrcb_0_0.xci" Type="IP">
+        <Instance HierarchyPath="v_rgb2ycrcb_0"/>
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
       <File Name="ip\Arty_Z7_20_s00_regslice_0\Arty_Z7_20_s00_regslice_0.xci" Type="IP">
         <Instance HierarchyPath="axi_mem_intercon/s00_couplers/s00_regslice"/>
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@@ -229,7 +293,7 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip\Arty_Z7_20_auto_pc_0\Arty_Z7_20_auto_pc_0.xci" Type="IP">
-        <Instance HierarchyPath="axi_mem_intercon/s00_couplers/auto_pc"/>
+        <Instance HierarchyPath="axi_mem_intercon/m00_couplers/auto_pc"/>
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>

diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc b/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc
@@ -7,8 +7,10 @@
 # of Vivado)
 ################################################################################
 create_clock -name sys_clock -period 8 [get_ports sys_clock]
+create_clock -name TMDS_In_clk_p -period 10 [get_ports TMDS_In_clk_p]
+create_clock -name TMDS_In_clk_n -period 10 [get_ports TMDS_In_clk_n]
 create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]
-create_clock -name processing_system7_0_FCLK_CLK1 -period 7 [get_pins processing_system7_0/FCLK_CLK1]
+create_clock -name processing_system7_0_FCLK_CLK1 -period 8.462 [get_pins processing_system7_0/FCLK_CLK1]
 create_clock -name processing_system7_0_FCLK_CLK2 -period 13 [get_pins processing_system7_0/FCLK_CLK2]
 create_clock -name processing_system7_0_FCLK_CLK3 -period 20 [get_pins processing_system7_0/FCLK_CLK3]
 

diff --git a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef