Latest yosys synthesis results in missing CGA characters

[schlae]

Using the 3-Nov-2021 build of oss-cad-suite-build results in the CGA text generation code not synthesizing correctly. Instead of a full character, each cell just displays a single column.

[avlixa]

Hi,
Try changing this in cga_pixel.v

// This must be a mux. Using a shift register causes very weird
// issues with the character ROM and Yosys turns it into a bunch
// of flip-flops instead of a ROM.
wire [2:0] charpix;
assign charpix = hres_mode ? (clk_seq[3:1] + 3'd6) : (clk_seq[4:2] + 3'd7);  

always @ (*)
begin
    if (video_enabled) begin
        // Hi-res vs low-res needs different adjustments
        //case (hres_mode ? (clk_seq[3:1] + 3'd6) : (clk_seq[4:2] + 3'd7))
        case (charpix)

It seems using the sentece directly in the case is generating a signal with more than 3 bits. I tried it in @spark2k06 ZXUncore version and it works.

[schlae]

Yes, this makes sense. The original design infers an adder and there's an ambiguity regarding the resulting bit width: looks like the newer versions of Yosys include the carry out which makes the mux 4 bits wide instead of 3. The result doesn't wrap correctly and triggers the default case for most of the clock sequence. I've pushed your recommended fix, thanks for looking at it!