Merge pull request chipsalliance#1947 from hzeller/20230613-add-calip…

…tra-smoke-test Add caliptra-rtl to smoke tests.
sconwayaus · Jun 13, 2023 · c719ed3 · c719ed3
2 parents 80d368c + a343042
commit c719ed3
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Showing 2 changed files with 31 additions and 21 deletions.
diff --git a/.github/bin/error-log-analyzer.py b/.github/bin/error-log-analyzer.py
@@ -137,6 +137,7 @@ def __str__(self):
             "https://github.com/lowRISC/opentitan",
             "https://github.com/chipsalliance/sv-tests",
             "https://github.com/chipsalliance/Cores-VeeR-EH2",
+            "https://github.com/chipsalliance/caliptra-rtl",
             "https://github.com/openhwgroup/cva6",
             "https://github.com/SymbiFlow/uvm",
             "https://github.com/taichi-ishitani/tnoc",

diff --git a/.github/bin/smoke-test.sh b/.github/bin/smoke-test.sh
@@ -83,6 +83,7 @@ readonly TEST_GIT_PROJECTS="https://github.com/lowRISC/ibex \
          https://github.com/lowRISC/opentitan \
          https://github.com/chipsalliance/sv-tests \
          https://github.com/chipsalliance/Cores-VeeR-EH2 \
+         https://github.com/chipsalliance/caliptra-rtl \
          https://github.com/openhwgroup/cva6 \
          https://github.com/SymbiFlow/uvm \
          https://github.com/taichi-ishitani/tnoc \
@@ -107,12 +108,15 @@ readonly TEST_GIT_PROJECTS="https://github.com/lowRISC/ibex \
 # Any new issues that arise should be recorded in the verible bug-tracker to
 # be fixed.
 # Goal: The following list shall be empty :)
+# Format: <tool-name>:<file-name>
 declare -A KnownIssue
 
 # At the moment, the list is empty
 
 #--- Too many to mention manually, so here we do the 'waive all' approach
+# Format: <tool-name>:<project>
 declare -A KnownProjectToolIssue
+KnownProjectToolIssue[project:caliptra-rtl]=https://github.com/chipsalliance/verible/issues/1946
 
 ##
 # Some tools still not fully process all files and return a non-zero exit
@@ -128,16 +132,21 @@ ExpectedFailCount[lint:ibex]=14
 ExpectedFailCount[project:ibex]=192
 ExpectedFailCount[preprocessor:ibex]=368
 
-ExpectedFailCount[syntax:opentitan]=35
-ExpectedFailCount[lint:opentitan]=35
-ExpectedFailCount[project:opentitan]=730
-ExpectedFailCount[preprocessor:opentitan]=1950
+ExpectedFailCount[syntax:opentitan]=36
+ExpectedFailCount[lint:opentitan]=36
+ExpectedFailCount[project:opentitan]=732
+ExpectedFailCount[preprocessor:opentitan]=1955
 
 ExpectedFailCount[syntax:sv-tests]=77
 ExpectedFailCount[lint:sv-tests]=76
 ExpectedFailCount[project:sv-tests]=187
 ExpectedFailCount[preprocessor:sv-tests]=139
 
+ExpectedFailCount[syntax:caliptra-rtl]=4
+ExpectedFailCount[lint:caliptra-rtl]=4
+ExpectedFailCount[project:caliptra-rtl]=288
+ExpectedFailCount[preprocessor:caliptra-rtl]=668
+
 ExpectedFailCount[syntax:Cores-VeeR-EH2]=2
 ExpectedFailCount[lint:Cores-VeeR-EH2]=2
 ExpectedFailCount[project:Cores-VeeR-EH2]=42
@@ -148,9 +157,9 @@ ExpectedFailCount[lint:cva6]=4
 ExpectedFailCount[project:cva6]=70
 ExpectedFailCount[preprocessor:cva6]=65
 
-ExpectedFailCount[syntax:uvm]=2
-ExpectedFailCount[lint:uvm]=2
-ExpectedFailCount[project:uvm]=44
+ExpectedFailCount[syntax:uvm]=1
+ExpectedFailCount[lint:uvm]=1
+ExpectedFailCount[project:uvm]=43
 ExpectedFailCount[preprocessor:uvm]=115
 
 ExpectedFailCount[syntax:tnoc]=3
@@ -161,28 +170,28 @@ ExpectedFailCount[preprocessor:tnoc]=57
 ExpectedFailCount[project:80x86]=2
 ExpectedFailCount[preprocessor:80x86]=7
 
-ExpectedFailCount[syntax:XilinxUnisimLibrary]=9
-ExpectedFailCount[lint:XilinxUnisimLibrary]=9
-ExpectedFailCount[project:XilinxUnisimLibrary]=27
+ExpectedFailCount[syntax:XilinxUnisimLibrary]=4
+ExpectedFailCount[lint:XilinxUnisimLibrary]=4
+ExpectedFailCount[project:XilinxUnisimLibrary]=22
 ExpectedFailCount[preprocessor:XilinxUnisimLibrary]=96
 
-ExpectedFailCount[syntax:black-parrot]=161
-ExpectedFailCount[lint:black-parrot]=161
-ExpectedFailCount[project:black-parrot]=175
-ExpectedFailCount[preprocessor:black-parrot]=176
+ExpectedFailCount[syntax:black-parrot]=156
+ExpectedFailCount[lint:black-parrot]=156
+ExpectedFailCount[project:black-parrot]=171
+ExpectedFailCount[preprocessor:black-parrot]=172
 
-ExpectedFailCount[syntax:ivtest]=168
-ExpectedFailCount[lint:ivtest]=168
-ExpectedFailCount[project:ivtest]=198
+ExpectedFailCount[syntax:ivtest]=166
+ExpectedFailCount[lint:ivtest]=166
+ExpectedFailCount[project:ivtest]=196
 ExpectedFailCount[preprocessor:ivtest]=26
 
 ExpectedFailCount[syntax:nontrivial-mips]=2
 ExpectedFailCount[lint:nontrivial-mips]=2
 ExpectedFailCount[project:nontrivial-mips]=81
 ExpectedFailCount[preprocessor:nontrivial-mips]=78
 
-ExpectedFailCount[project:axi]=69
-ExpectedFailCount[preprocessor:axi]=66
+ExpectedFailCount[project:axi]=71
+ExpectedFailCount[preprocessor:axi]=68
 
 ExpectedFailCount[syntax:rsd]=5
 ExpectedFailCount[lint:rsd]=5
@@ -195,8 +204,8 @@ ExpectedFailCount[preprocessor:scr1]=46
 ExpectedFailCount[project:serv]=1
 ExpectedFailCount[preprocessor:serv]=1
 
-ExpectedFailCount[syntax:basejump_stl]=467
-ExpectedFailCount[lint:basejump_stl]=467
+ExpectedFailCount[syntax:basejump_stl]=466
+ExpectedFailCount[lint:basejump_stl]=466
 ExpectedFailCount[project:basejump_stl]=577
 ExpectedFailCount[preprocessor:basejump_stl]=610