risc-v: switch to hart1 #68
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revised from 59 |
elfloader-tool/src/arch-riscv/crt0.S
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| @@ -24,7 +28,7 @@ _start: | |||
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| /* OpenSBI starts all HARTs and sends them to this entry point. */ | |||
| li s0, CONFIG_FIRST_HART_ID | |||
| bne a0, s0, secondary_harts | |||
| bne a0, s0, switch_heart | |||
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| bne a0, s0, switch_heart | |
| bne a0, s0, switch_hart |
elfloader-tool/src/arch-riscv/crt0.S
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| @@ -41,6 +45,14 @@ bootstack_secondary_cores: | |||
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| .text | |||
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| switch_heart: | |||
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| switch_heart: | |
| switch_hart: |
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What is supposed to happen if the bootloader only supports the legacy SBI extension? |
Should we even support the legacy SBI extension? I can add a check to call the existing code based on the SBI version or something like this. |
The only SBI calls that we currently use are legacy SBI extensions: https://github.com/seL4/seL4/blob/master/include/arch/riscv/arch/sbi.h#L38 This allows the kernel to still be used with older SBI implementations such as the BBL.
I think that is a good idea. |
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Sorry I should have been a bit more clear.
Do we want to support BBL? I suppose it wont hurt, but I don't see why people would be using it over more mature alternatives. I don't have that much context though. That is the only reason they exist, but are now depreciated in favor of the listed exts here. I suppose our code could more accurately reflect that each call is a separate extension, if I understand it correctly. |
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I'd propose that you can select the SBI implementation. That is how I am using this at the moment. Depending what SBI you have, this defnes how the commands are actually implemented. Then we don'*t have to worry about the details now. I can make a PR with my changes for SBI selection. |
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Ok @kent-mcleod I've added the check |
elfloader-tool/src/arch-riscv/crt0.S
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| otherwise rely on the legacy extension */ | ||
| jal spi_probe_extension | ||
| li s0, 1 | ||
| blt x1, s0, secondary_harts |
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please add a bit info about what value is returned by spi_probe_extension and why the value is compared with 1.
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so if the extension is not supported, the current hart is not hart1, and SMP is not enabled, the hart just spins. Is that the expected results?
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Yes that's right. BBL worked like this. If using OPENSBI this code path shouldn't be used.
| @@ -5,7 +5,7 @@ | |||
| */ | |||
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| #include <elfloader_common.h> | |||
| #include "sbi.h" | |||
| #include <sbi.h> | |||
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This should be in another commit?
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Or this change can be dropped as it doesn't affect the rest of the PR I believe.
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Yeah thought I would just fix it up. Not sure if it was intended.
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@oliver-wm: Are you able to create some riscv SMP test configurations for the CI? |
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Conceptually, how does this work with SMP? Suppose we're lucky and openSBI starts elfloader with hart 1/CONFIG_FIRST_HART_ID. Is elfloader supposed to start up all secondary cores and have them spin until sel4 gives a IPI? Or is that delegated to the seL4 kernel? A couple of details about why I'm asking this: I'm trying to get SMP running on the hifive board with openSBI. My test application is sel4test with SMP support enabled ( |
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Yes, elfloader starts the other cores now once main has initialised from hart 1.
I've just fixed a bug with the registers, some parameters were added to the elfloader code and the kernel code was never updated. So this should fix your issue. See seL4/seL4@baad619 |
seL4 and librarys assume booting on hart 1 while Opensbi and U-boot pick a hart at random. This patch uses the HSM SBI call (if it exisits) to start the elfloader on hart1 if a different hart has been chosen. If SMP is enabled it now starts all harts with the HSM extension from boot.c. Credits go to Peter Chubb for initial spike. Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
seL4 and librarys assume booting on hart1 while
Opensbi and U-boot pick a hart at random.
This patch uses an SBI call to start the elfloader on hart1
if a different hart has been choses.
Credits go to Peter Chubb for the straw-man example.
Signed-off-by: Oliver Scott Oliver.Scott@data61.csiro.au