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riscv: Add clear_bss to crt0 if image is binary #82

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merged 3 commits into from
Jun 7, 2021
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nomadeel
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@nomadeel nomadeel commented Jun 3, 2021

Binary images do not have the luxury of having a proper loader load
the elfloader into memory correctly and zero out the BSS, so we have to
do it ourselves.

Signed-off-by: Damon Lee Damon.Lee@data61.csiro.au

Binary images do not have the luxury of having a proper loader load
the elfloader into memory correctly and zero out the BSS, so we have to
do it ourselves.

Signed-off-by: Damon Lee <Damon.Lee@data61.csiro.au>
@nomadeel nomadeel requested a review from axel-h June 3, 2021 05:24
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Where is clear bss?

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nomadeel commented Jun 3, 2021

The SBI call clobbers a0 which is needed for the secondary_hart routine
to check what the ID is of the HART that is currently running.

Signed-off-by: Damon Lee <Damon.Lee@data61.csiro.au>
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nomadeel commented Jun 3, 2021

Added an extra commit for a fix that I found as well.

@nomadeel nomadeel requested a review from kent-mcleod June 4, 2021 02:23
t3 is a temporary register and s0 is always preserved across calls (C
function calls and ecalls) so we use s0 instead of a temporary register
like t3.

Signed-off-by: Damon Lee <Damon.Lee@data61.csiro.au>
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nomadeel commented Jun 7, 2021

Added a commit to use s0 instead of t3 for the HART ID.

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nomadeel commented Jun 7, 2021

Can I get a review for this? I'm close to getting a release done and this is one of the blockers.

@nomadeel nomadeel merged commit 4ca410b into master Jun 7, 2021
@nomadeel nomadeel deleted the riscv_zero_bss branch June 7, 2021 06:05
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4 participants