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The top lvl TCL scripts marked 'ES' for engineering sample have been merged with the scripts for standard devices - 'PS' for production silicon. There are now 3 top lvl TCL scripts in the main Libero_Projects folder instead of 6. An additional argument has been created to allow users to build designs for 'ES' die targets. If 'ES' or 'es' is passed in as the 3rd argument, the Libero design will build for an 'ES' target. Otherwise, 'PS' is the default option. The argument can also be passed in in the 2nd argument space if no design flow argument was needed. The top lvl TCL files have been revamped. Dynamic links are now used to compose project files and name. Script messaging has been improved and the messages have been categorized into warnings, errors and info messages. Top lvl TCL also updated to allow 'ES' die selection for DGC2 design. Lower lvl TCL and READMEs updates to follow. Author: Sebastian Slowikowski <seb.slowikowski@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
The low TCL scripts for importing components and constraints have been renamed and had their names shortened. DGC2 design also had file name changes applied to it. - CoreAHBlite DirectCore has been updated in CFG designs. Component version updated from v5.5.105 to 5.6.105. - A missing connection was added in CFG designs for "FPGA_POR_ON" signal, between PF_INIT_MONITOR and CoreRESET_PF. - Re-arrange SmartDesign layout command was added to CFG designs.Command runs at the end of base design build for a cleaner SmartDesign layout look. Note: New PF_INIT_MONITOR SgCore is successfully downloaded and instantiated in the designs if they are ran in latest Libero SoC v2022.1. This is an automatic process, achieved by use of wild cards defined for SgCore component version numbers. Author: Sebastian Slowikowski <seb.slowikowski@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
The readme file:./Libero_Projects/README.md was showing the wrong number of 'Internal IRQs' for the 3 configurations available for MIV_RV32. The number was changed from 6 to 1. The designs used to support 6 'Internal IRQs' up until v12.6 release of the scripts, when that number was reduced to 1 as, no more interrupts were needed. The readmes have been updated with information on the new 3rd argument.It was implemented to allow design building targeted for an 'ES' die type. Other minor fixes were made to the readme files. Readme for DGC2 design has also been updated, to reflect how the 3rd argument can be used to build an 'ES' die type design for the configuration. All readmes have been updated to now show that the latest Libero SoC v2022.1 is supported. Author: Sebastian Slowikowski <seb.slowikowski@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
New bitstreams/programming files for both 'PS' and 'ES' die type devices have been re-generated in the latest Libero SoC v2022.1. 'ES' bitstream is now provided for the DGC2 design. Author: Merijn van de Water<Merijn.vandeWater@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
The ./Libero_Projects/README.md (as well as DGC2 readme) had the 'PS' and 'ES' argument entries removed from the 2nd argument table as to avoid confusion. Other wording relating to die type has been improved. Author: Sebastian Slowikowski <seb.slowikowski@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
Update for Lib. v2022.1 Merging candidate for release 2022.1-v1
Merging develop into main - Libero v2022.1 designs
seb-slowik
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Jul 2, 2023
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