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msp430 [bf]: regularize msp430usci.h between x5 and x2
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make x2xxx/usci-bf/msp430usci.h and x5xxx version reasonably similar.
We want to try to keep them the same.
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@cire831
cire831 committed May 23, 2012
1 parent 4332a46 commit f8a20b3
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Showing 2 changed files with 105 additions and 69 deletions.
70 changes: 48 additions & 22 deletions tos/chips/msp430/x2xxx/usci-bf/msp430usci.h
View file
Expand Up @@ -3,6 +3,20 @@

#include "msp430hardware.h"

#ifndef UCSSEL__SMCLK
/*
* Both the x2 and x5 families have UCSIs and need a clock source.
* The x5 cpu header files define UCSSEL__SMCLK but the x2 headers
* don't (please TI, can you be more consistent?... nah. that's
* fine, we'll deal)
*
* Note: this is x2xxx/usci/msp430usci.h and is inherently a
* x2 file.
*/
#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
#endif

/* MSP430_USCI_RESOURCE is used for USCI_IDs */
#define MSP430_USCI_RESOURCE "Msp430Usci.Resource"

#define MSP430_USCI_A0_RESOURCE "Msp430Usci.A0.Resource"
Expand All @@ -27,49 +41,61 @@ enum {
* Mode-specific configuration data should be provided elsewise.
*/
typedef struct msp430_usci_config_t {
uint8_t ctl0;
uint8_t ctl1;
uint8_t br0;
uint8_t br1;
uint8_t ctl0; /* various control bits, msb */
uint8_t ctl1; /* clock select and swreset, lsb */
uint8_t br0; /* lsb divider */
uint8_t br1; /* msb divider */
uint8_t mctl;
uint16_t i2coa;
} msp430_usci_config_t;

//see note in Msp430UsciI2CP.nc I2CBasicAddr.read
#define I2C_ONE_BYTE_READ_COUNTER 0xE00
// see note in Msp430UsciI2CP.nc I2CBasicAddr.read
// x5 uses 0x500, x2 uses 0xe00 can they be the same?
#define I2C_ONE_BYTE_READ_COUNTER 0x0E00

#ifndef TOS_DEFAULT_BAUDRATE
#define TOS_DEFAULT_BAUDRATE 115200
#endif /* TOS_DEFAULT_BAUDRATE */


/*
* The following default configurations assume SMCLK clock is 1MiHz (2^20Hz).
*/

msp430_usci_config_t msp430_usci_uart_default_config = {
/* N81 UART mode driven by SMCLK */
ctl0 : 0,
ctl1 : UCSSEL_SMCLK,
ctl1 : UCSSEL__SMCLK,

/* SLAU259 Table 16-4 2^20Hz 115200: UBR=9, BRS=1, BRF=0 */
br0 : 9, // 115200
br1 : 0,
mctl : UCBRF_0 + UCBRS_1
br0 : 9,
br1 : 0,
mctl : UCBRF_0 | UCBRS_1,
i2coa: 0
};

msp430_usci_config_t msp430_usci_spi_default_config = {
/* Inactive high MSB-first 8-bit 3-pin master driven by SMCLK */
ctl0 : UCSSEL_SMCLK,
ctl1 : UCCKPL | UCMSB | UCMST | UCSYNC,
/* 2x Prescale */
br0 : 2,
br1 : 0,
mctl : 0 /* Always 0 in SPI mode */
ctl0 : UCCKPL | UCMSB | UCMST | UCSYNC,
ctl1 : UCSSEL__SMCLK,
br0 : 2, /* 2x Prescale */
br1 : 0,
mctl : 0,
i2coa: 0
};

// Should the default be the following? MM (multi-master) seems
// like it should be a platform specific thing.
// ctl0 : (UCMST | UCMODE_3 | UCSYNC),

msp430_usci_config_t msp430_usci_i2c_default_config = {
ctl0: UCSYNC|UCMODE_3|UCMM,
ctl1: UCSSEL_2,
br0: 0x08,
br1: 0x00,
mctl: 0x00,
i2coa: 'A',
/* 7 bit addressing single I2C master driven by SMCLK */
ctl0 : UCSYNC | UCMODE_3 | UCMM,
ctl1 : UCSSEL__SMCLK,
br0 : 10, /* 104857 hz, slow for slow devices. */
br1 : 0,
mctl : 0,
i2coa: 0x41,
};

enum {
Expand Down
104 changes: 57 additions & 47 deletions tos/chips/msp430/x5xxx/usci-bf/msp430usci.h
View file
Expand Up @@ -3,6 +3,19 @@

#include "msp430hardware.h"

#ifndef UCSSEL__SMCLK
/*
* Both the x2 and x5 families have UCSIs and need a clock source.
* The x5 cpu header files define UCSSEL__SMCLK but the x2 headers
* don't (please TI, can you be more consistent?... nah. that's
* fine, we'll deal)
*
* Note: this is x2xxx/usci/msp430usci.h and is inherently a
* x2 file.
*/
#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
#endif

/* MSP430_USCI_RESOURCE is used for USCI_IDs */
#define MSP430_USCI_RESOURCE "Msp430Usci.Resource"

Expand All @@ -28,76 +41,88 @@ enum {
* Mode-specific configuration data should be provided elsewise.
*/
typedef struct msp430_usci_config_t {
uint8_t ctl0; /* most significant, order swapped */
uint8_t ctl1;
uint8_t br1; /* most significant */
uint8_t br0;
uint8_t mctl;
uint8_t ctl0; /* various control bits, msb */
uint8_t ctl1; /* clock select and swreset, lsb */
uint8_t br0; /* lsb divider */
uint8_t br1; /* msb divider */
uint8_t mctl;
uint16_t i2coa;
} msp430_usci_config_t;


//see note in Msp430UsciI2CP.nc I2CBasicAddr.read
#define I2C_ONE_BYTE_READ_COUNTER 0x500

// see note in Msp430UsciI2CP.nc I2CBasicAddr.read
// x5 uses 0x500, x2 uses 0xe00 can they be the same?
#define I2C_ONE_BYTE_READ_COUNTER 0x0500

#ifndef TOS_DEFAULT_BAUDRATE
#define TOS_DEFAULT_BAUDRATE 115200
#endif /* TOS_DEFAULT_BAUDRATE */


/*
* This table assumes UART clock input (SMCLK) is 1MiHz (2^20Hz).
* The following default configurations assume SMCLK clock is 1MiHz (2^20Hz).
*/

msp430_usci_config_t msp430_usci_uart_default_config = {
/* N81 UART mode driven by SMCLK */
ctl0 : 0, /* note order flipped */
ctl1 : UCSSEL_SMCLK,
ctl0 : 0,
ctl1 : UCSSEL__SMCLK,

#if 9600 == TOS_DEFAULT_BAUDRATE
/* SLAU259 Table 16-4 2^20Hz 9600: UBR=109, BRS=2, BRF=0 */
br0 : 109,
br1 : 0,
br0 : 109, // 9600
mctl : UCBRF_0 + UCBRS_2,
mctl : UCBRF_0 | UCBRS_2,
#elif 19200 == TOS_DEFAULT_BAUDRATE
/* SLAU259 Table 16-4 2^20Hz 19200: UBR=54, BRS=2, BRF=0 */
br0 : 54,
br1 : 0,
br0 : 54, // 19200
mctl : UCBRF_0 + UCBRS_2,
mctl : UCBRF_0 | UCBRS_2,
#elif 38400 == TOS_DEFAULT_BAUDRATE
/* SLAU259 Table 16-4 2^20Hz 38400: UBR=27, BRS=2, BRF=0 */
br0 : 27,
br1 : 0,
br0 : 27, // 38400
mctl : UCBRF_0 + UCBRS_2,
mctl : UCBRF_0 | UCBRS_2,
#elif 57600 == TOS_DEFAULT_BAUDRATE
/* SLAU259 Table 16-4 2^20Hz 57600: UBR=18, BRS=1, BRF=0 */
br0 : 18,
br1 : 0,
br0 : 18, // 57600
mctl : UCBRF_0 + UCBRS_1,
mctl : UCBRF_0 | UCBRS_1,
#elif 115200 == TOS_DEFAULT_BAUDRATE
/* SLAU259 Table 16-4 2^20Hz 115200: UBR=9, BRS=1, BRF=0 */
br0 : 9,
br1 : 0,
br0 : 9, // 115200
mctl : UCBRF_0 + UCBRS_1,
mctl : UCBRF_0 | UCBRS_1,
#else
#warning Unrecognized value for TOS_DEFAULT_BAUDRATE, using 115200
br0 : 9,
br1 : 0,
br0 : 9, // 115200
mctl : UCBRF_0 + UCBRS_1,
mctl : UCBRF_0 | UCBRS_1,
#endif
i2c0a : 0
i2coa: 0
};

msp430_usci_config_t msp430_usci_spi_default_config = {
/* Inactive high MSB-first 8-bit 3-pin master driven by SMCLK */
ctl0 : (UCCKPL + UCMSB + UCMST + UCSYNC),
ctl1 : UCSSEL__SMCLK,
/* 2x Prescale */
br1 : 0,
br0 : 2,
mctl : 0, /* Always 0 in SPI mode */
i2coa : 0
ctl0 : UCCKPL | UCMSB | UCMST | UCSYNC,
ctl1 : UCSSEL__SMCLK,
br0 : 2, /* 2x Prescale */
br1 : 0,
mctl : 0,
i2coa: 0
};

// Should the default be the following? MM (multi-master) seems
// like it should be a platform specific thing.
// ctl0 : (UCMST | UCMODE_3 | UCSYNC),

msp430_usci_config_t msp430_usci_i2c_default_config = {
/* 7 bit addressing single I2C master driven by SMCLK */
ctl0 : UCSYNC | UCMODE_3 | UCMM,
ctl1 : UCSSEL__SMCLK,
br0 : 10, /* 104857 hz, slow for slow devices. */
br1 : 0,
mctl : 0,
i2coa: 0x41,
};

enum {
Expand All @@ -116,19 +141,4 @@ enum {
MSP430_USCI_ERR_UCxySTAT = MSP430_USCI_ERR_Framing | MSP430_USCI_ERR_Overrun | MSP430_USCI_ERR_Parity,
};


/*
* I2C default config, added by Derek Baker (derek@red-slate.com)
*/

msp430_usci_config_t msp430_usci_i2c_default_config = {
/* 7 bit addressing single I2C master driven by SMCLK */
ctl0 : (UCMST | UCMODE_3 | UCSYNC),
ctl1 : UCSSEL__SMCLK,
br1 : 0,
br0 : 10, /* gives us 103680 hz, slow speed but will work with all devices.*/
mctl : 0, /* Not used in I2C mode*/
i2coa : 'a'
};

#endif // _H_Msp430Usci_h

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