[-] Return target_cfg file back. Without it it is impossible to chang…

…e C++ template parameters using generic parameter and as a result properly configure systemc soc by changing top level configuration. SystemVerilog will be updated with the next commit
sergeykhbr · Nov 22, 2023 · 5727704 · 5727704
1 parent 19e0399
commit 5727704
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Showing 21 changed files with 109 additions and 265 deletions.
diff --git a/sc/prj/impl/asic/asic_top.cpp b/sc/prj/impl/asic/asic_top.cpp
@@ -19,8 +19,6 @@
 
 namespace debugger {
 
-static std::string CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";
-
 asic_top::asic_top(sc_module_name name,
                    int sim_uart_speedup_rate)
     : sc_module(name),
@@ -121,17 +119,6 @@ asic_top::asic_top(sc_module_name name,
 
 
     soc0 = new riscv_soc("soc0", async_reset,
-                          CFG_CPU_NUM,
-                          CFG_ILOG2_NWAYS,
-                          CFG_ILOG2_LINES_PER_WAY,
-                          CFG_DLOG2_NWAYS,
-                          CFG_DLOG2_LINES_PER_WAY,
-                          CFG_L2CACHE_ENA,
-                          CFG_L2_LOG2_NWAYS,
-                          CFG_L2_LOG2_LINES_PER_WAY,
-                          CFG_BOOTROM_LOG2_SIZE,
-                          CFG_SRAM_LOG2_SIZE,
-                          CFG_BOOTROM_FILE_HEX,
                           sim_uart_speedup_rate);
     soc0->i_sys_nrst(w_sys_nrst);
     soc0->i_sys_clk(w_sys_clk);

diff --git a/sc/prj/impl/asic/asic_top.h b/sc/prj/impl/asic/asic_top.h
@@ -23,6 +23,7 @@
 #include "../../../rtl/riverlib/river_cfg.h"
 #include "../../../rtl/sdctrl/sdctrl_cfg.h"
 #include "../../../rtl/riverlib/types_river.h"
+#include "target_cfg.h"
 #include "../../../rtl/techmap/bufg/ids_tech.h"
 #include "../../../rtl/techmap/bufg/iobuf_tech.h"
 #include "../../../rtl/techmap/pll/SysPLL_tech.h"
@@ -71,31 +72,6 @@ SC_MODULE(asic_top) {
     int sim_uart_speedup_rate_;
 
     static const bool async_reset = 0;
-
-    // @brief   Number of processors in a system
-    // @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
-    static const int CFG_CPU_NUM = 1;
-
-    // @brief Caches size parameters.
-    // @note Caches line size configured in river_cfg file and affects L1 memory bus width.
-    static const int CFG_ILOG2_LINES_PER_WAY = 7;
-    static const int CFG_ILOG2_NWAYS = 2;
-
-    static const int CFG_DLOG2_LINES_PER_WAY = 7;
-    static const int CFG_DLOG2_NWAYS = 2;
-
-    // @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
-    static const int CFG_L2CACHE_ENA = 1;
-    static const int CFG_L2_LOG2_NWAYS = 4;
-    static const int CFG_L2_LOG2_LINES_PER_WAY = 9;
-
-    // Internal Boot ROM size:
-    static const int CFG_BOOTROM_LOG2_SIZE = 16;
-
-    // Internal SRAM block:
-    //     - Increase memory map if need > 2MB FU740
-    //     - Change bootloader stack pointer if need less than 512 KB
-    static const int CFG_SRAM_LOG2_SIZE = 21;
 
     sc_signal<bool> ib_clk_tcxo;
     sc_signal<sc_uint<12>> ib_gpio_ipins;

diff --git a/sc/prj/impl/asic/target_cfg.h b/sc/prj/impl/asic/target_cfg.h
@@ -0,0 +1,52 @@
+// 
+//  Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
+// 
+//  Licensed under the Apache License, Version 2.0 (the "License");
+//  you may not use this file except in compliance with the License.
+//  You may obtain a copy of the License at
+// 
+//      http://www.apache.org/licenses/LICENSE-2.0
+// 
+//  Unless required by applicable law or agreed to in writing, software
+//  distributed under the License is distributed on an "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//  See the License for the specific language governing permissions and
+//  limitations under the License.
+// 
+#pragma once
+
+#include <systemc.h>
+
+namespace debugger {
+
+
+// @brief   Number of processors in a system
+// @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
+static const int CFG_CPU_NUM = 1;
+
+// @brief Caches size parameters.
+// @note Caches line size configured in river_cfg file and affects L1 memory bus width.
+static const int CFG_ILOG2_LINES_PER_WAY = 7;               // I$ length: 7=16KB; 8=32KB; ..
+static const int CFG_ILOG2_NWAYS = 2;                       // I$ associativity. Default bits width = 2, means 4 ways
+
+static const int CFG_DLOG2_LINES_PER_WAY = 7;               // D$ length: 7=16KB; 8=32KB; ..
+static const int CFG_DLOG2_NWAYS = 2;                       // D$ associativity. Default bits width = 2, means 4 ways
+
+// @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
+static const int CFG_L2CACHE_ENA = 1;
+static const int CFG_L2_LOG2_NWAYS = 4;
+static const int CFG_L2_LOG2_LINES_PER_WAY = 9;             // 7=16KB; 8=32KB; 9=64KB, ..
+
+// Internal Boot ROM size:
+static const int CFG_BOOTROM_LOG2_SIZE = 16;                // 16=64 KB (default); 17=128KB; ..
+
+// Project relative HEX-file name to init boot ROM without .hex extension:
+static const std::string CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";
+
+// Internal SRAM block:
+//     - Increase memory map if need > 2MB FU740
+//     - Change bootloader stack pointer if need less than 512 KB
+static const int CFG_SRAM_LOG2_SIZE = 21;                   // 19=512 KB (KC705); 21=2 MB (ASIC); ..
+
+}  // namespace debugger
+
diff --git a/sc/rtl/riscv_soc.cpp b/sc/rtl/riscv_soc.cpp
@@ -21,17 +21,6 @@ namespace debugger {
 
 riscv_soc::riscv_soc(sc_module_name name,
                      bool async_reset,
-                     uint32_t cpu_num,
-                     uint32_t ilog2_nways,
-                     uint32_t ilog2_lines_per_way,
-                     uint32_t dlog2_nways,
-                     uint32_t dlog2_lines_per_way,
-                     uint32_t l2cache_ena,
-                     uint32_t l2log2_nways,
-                     uint32_t l2log2_lines_per_way,
-                     uint32_t bootrom_log2_size,
-                     uint32_t sram_log2_size,
-                     std::string bootfile,
                      int sim_uart_speedup_rate)
     : sc_module(name),
     i_sys_nrst("i_sys_nrst"),
@@ -92,17 +81,6 @@ riscv_soc::riscv_soc(sc_module_name name,
     dev_pnp("dev_pnp", SOC_PNP_TOTAL) {
 
     async_reset_ = async_reset;
-    cpu_num_ = cpu_num;
-    ilog2_nways_ = ilog2_nways;
-    ilog2_lines_per_way_ = ilog2_lines_per_way;
-    dlog2_nways_ = dlog2_nways;
-    dlog2_lines_per_way_ = dlog2_lines_per_way;
-    l2cache_ena_ = l2cache_ena;
-    l2log2_nways_ = l2log2_nways;
-    l2log2_lines_per_way_ = l2log2_lines_per_way;
-    bootrom_log2_size_ = bootrom_log2_size;
-    sram_log2_size_ = sram_log2_size;
-    bootfile_ = bootfile;
     sim_uart_speedup_rate_ = sim_uart_speedup_rate;
     bus0 = 0;
     bus1 = 0;
@@ -141,14 +119,8 @@ riscv_soc::riscv_soc(sc_module_name name,
 
 
     group0 = new Workgroup("group0", async_reset,
-                            cpu_num,
-                            ilog2_nways,
-                            ilog2_lines_per_way,
-                            dlog2_nways,
-                            dlog2_lines_per_way,
-                            l2cache_ena,
-                            l2log2_nways,
-                            l2log2_lines_per_way);
+                            CFG_CPU_NUM,
+                            CFG_L2CACHE_ENA);
     group0->i_cores_nrst(i_sys_nrst);
     group0->i_dmi_nrst(i_dbg_nrst);
     group0->i_clk(i_sys_clk);
@@ -174,8 +146,8 @@ riscv_soc::riscv_soc(sc_module_name name,
     group0->o_dmreset(o_dmreset);
 
 
-    rom0 = new axi_rom<16>("rom0", async_reset,
-                           bootfile);
+    rom0 = new axi_rom<CFG_BOOTROM_LOG2_SIZE>("rom0", async_reset,
+                                              CFG_BOOTROM_FILE_HEX);
     rom0->i_clk(i_sys_clk);
     rom0->i_nrst(i_sys_nrst);
     rom0->i_mapinfo(bus0_mapinfo[CFG_BUS0_XSLV_BOOTROM]);
@@ -184,7 +156,7 @@ riscv_soc::riscv_soc(sc_module_name name,
     rom0->o_xslvo(axiso[CFG_BUS0_XSLV_BOOTROM]);
 
 
-    sram0 = new axi_sram<21>("sram0", async_reset);
+    sram0 = new axi_sram<CFG_SRAM_LOG2_SIZE>("sram0", async_reset);
     sram0->i_clk(i_sys_clk);
     sram0->i_nrst(i_sys_nrst);
     sram0->i_mapinfo(bus0_mapinfo[CFG_BUS0_XSLV_SRAM]);
@@ -287,8 +259,8 @@ riscv_soc::riscv_soc(sc_module_name name,
 
     pnp0 = new apb_pnp<SOC_PNP_TOTAL>("pnp0", async_reset,
                                       SOC_HW_ID,
-                                      cpu_num,
-                                      l2cache_ena,
+                                      CFG_CPU_NUM,
+                                      CFG_L2CACHE_ENA,
                                       SOC_PLIC_IRQ_TOTAL);
     pnp0->i_clk(i_sys_clk);
     pnp0->i_nrst(i_sys_nrst);

diff --git a/sc/rtl/riscv_soc.h b/sc/rtl/riscv_soc.h
@@ -23,6 +23,7 @@
 #include "riverlib/river_cfg.h"
 #include "sdctrl/sdctrl_cfg.h"
 #include "riverlib/types_river.h"
+#include "../prj/impl/asic/target_cfg.h"
 #include "ambalib/axictrl_bus0.h"
 #include "ambalib/axi2apb_bus1.h"
 #include "misclib/axi_rom.h"
@@ -101,35 +102,13 @@ SC_MODULE(riscv_soc) {
 
     riscv_soc(sc_module_name name,
               bool async_reset,
-              uint32_t cpu_num,
-              uint32_t ilog2_nways,
-              uint32_t ilog2_lines_per_way,
-              uint32_t dlog2_nways,
-              uint32_t dlog2_lines_per_way,
-              uint32_t l2cache_ena,
-              uint32_t l2log2_nways,
-              uint32_t l2log2_lines_per_way,
-              uint32_t bootrom_log2_size,
-              uint32_t sram_log2_size,
-              std::string bootfile,
               int sim_uart_speedup_rate);
     virtual ~riscv_soc();
 
     void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
 
  private:
     bool async_reset_;
-    uint32_t cpu_num_;
-    uint32_t ilog2_nways_;
-    uint32_t ilog2_lines_per_way_;
-    uint32_t dlog2_nways_;
-    uint32_t dlog2_lines_per_way_;
-    uint32_t l2cache_ena_;
-    uint32_t l2log2_nways_;
-    uint32_t l2log2_lines_per_way_;
-    uint32_t bootrom_log2_size_;
-    uint32_t sram_log2_size_;
-    std::string bootfile_;
     int sim_uart_speedup_rate_;
 
 
@@ -176,8 +155,8 @@ SC_MODULE(riscv_soc) {
 
     axictrl_bus0 *bus0;
     axi2apb_bus1 *bus1;
-    axi_rom<16> *rom0;
-    axi_sram<21> *sram0;
+    axi_rom<CFG_BOOTROM_LOG2_SIZE> *rom0;
+    axi_sram<CFG_SRAM_LOG2_SIZE> *sram0;
     clint<CFG_CPU_MAX> *clint0;
     plic<SOC_PLIC_CONTEXT_TOTAL, SOC_PLIC_IRQ_TOTAL> *plic0;
     apb_uart<SOC_UART1_LOG2_FIFOSZ> *uart1;

diff --git a/sc/rtl/riverlib/cache/cache_top.cpp b/sc/rtl/riverlib/cache/cache_top.cpp
@@ -21,11 +21,7 @@ namespace debugger {
 
 CacheTop::CacheTop(sc_module_name name,
                    bool async_reset,
-                   bool coherence_ena,
-                   uint32_t ilog2_nways,
-                   uint32_t ilog2_lines_per_way,
-                   uint32_t dlog2_nways,
-                   uint32_t dlog2_lines_per_way)
+                   bool coherence_ena)
     : sc_module(name),
     i_clk("i_clk"),
     i_nrst("i_nrst"),
@@ -85,19 +81,13 @@ CacheTop::CacheTop(sc_module_name name,
 
     async_reset_ = async_reset;
     coherence_ena_ = coherence_ena;
-    ilog2_nways_ = ilog2_nways;
-    ilog2_lines_per_way_ = ilog2_lines_per_way;
-    dlog2_nways_ = dlog2_nways;
-    dlog2_lines_per_way_ = dlog2_lines_per_way;
     i1 = 0;
     d0 = 0;
     pma0 = 0;
     pmp0 = 0;
     queue0 = 0;
 
-    i1 = new ICacheLru("i1", async_reset,
-                        ilog2_nways,
-                        ilog2_lines_per_way);
+    i1 = new ICacheLru("i1", async_reset);
     i1->i_clk(i_clk);
     i1->i_nrst(i_nrst);
     i1->i_req_valid(i_req_ctrl_valid);
@@ -126,8 +116,6 @@ CacheTop::CacheTop(sc_module_name name,
 
 
     d0 = new DCacheLru("d0", async_reset,
-                        dlog2_nways,
-                        dlog2_lines_per_way,
                         coherence_ena);
     d0->i_clk(i_clk);
     d0->i_nrst(i_nrst);

diff --git a/sc/rtl/riverlib/cache/cache_top.h b/sc/rtl/riverlib/cache/cache_top.h
@@ -17,6 +17,7 @@
 
 #include <systemc.h>
 #include "../river_cfg.h"
+#include "../../../prj/impl/asic/target_cfg.h"
 #include "icache_lru.h"
 #include "dcache_lru.h"
 #include "pma.h"
@@ -95,22 +96,14 @@ SC_MODULE(CacheTop) {
 
     CacheTop(sc_module_name name,
              bool async_reset,
-             bool coherence_ena,
-             uint32_t ilog2_nways,
-             uint32_t ilog2_lines_per_way,
-             uint32_t dlog2_nways,
-             uint32_t dlog2_lines_per_way);
+             bool coherence_ena);
     virtual ~CacheTop();
 
     void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
 
  private:
     bool async_reset_;
     bool coherence_ena_;
-    uint32_t ilog2_nways_;
-    uint32_t ilog2_lines_per_way_;
-    uint32_t dlog2_nways_;
-    uint32_t dlog2_lines_per_way_;
 
     static const int DATA_PATH = 0;
     static const int CTRL_PATH = 1;

diff --git a/sc/rtl/riverlib/cache/dcache_lru.cpp b/sc/rtl/riverlib/cache/dcache_lru.cpp
@@ -21,8 +21,6 @@ namespace debugger {
 
 DCacheLru::DCacheLru(sc_module_name name,
                      bool async_reset,
-                     uint32_t waybits,
-                     uint32_t ibits,
                      bool coherence_ena)
     : sc_module(name),
     i_clk("i_clk"),
@@ -68,16 +66,12 @@ DCacheLru::DCacheLru(sc_module_name name,
     o_flush_end("o_flush_end") {
 
     async_reset_ = async_reset;
-    waybits_ = waybits;
-    ibits_ = ibits;
     coherence_ena_ = coherence_ena;
-    ways = (1 << waybits);
-    FLUSH_ALL_VALUE = ((1 << (ibits + waybits)) - 1);
     mem0 = 0;
 
     mem0 = new TagMemNWay<abus,
-                          2,
-                          7,
+                          CFG_DLOG2_NWAYS,
+                          CFG_DLOG2_LINES_PER_WAY,
                           lnbits,
                           flbits,
                           1>("mem0", async_reset);
@@ -361,7 +355,7 @@ void DCacheLru::comb() {
     }
 
     // Flush counter when direct access
-    if (r.req_addr.read()((waybits_ - 1), 0) == (ways - 1)) {
+    if (r.req_addr.read()((CFG_DLOG2_NWAYS - 1), 0) == (ways - 1)) {
         vb_addr_direct_next = ((r.req_addr.read() + L1CACHE_BYTES_PER_LINE)
                 & (~LINE_BYTES_MASK));
     } else {