[*] Make codeid generic parameter in TAP as template in sysc

[*] rtlgen update: Cleanup empty spaces at the end of emtpy string
sergeykhbr · Nov 26, 2023 · 8994714 · 8994714
1 parent 831c6cd
commit 8994714
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Showing 18 changed files with 59 additions and 51 deletions.
diff --git a/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h b/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h
@@ -84,7 +84,7 @@ SC_MODULE(vip_sdcard_ctrl) {
     static const uint8_t SDSTATE_PRG = 7;
     static const uint8_t SDSTATE_DIS = 8;
     static const uint8_t SDSTATE_INA = 9;
-    
+
     // Data block access state machine:
     static const uint8_t DATASTATE_IDLE = 0;
     static const uint8_t DATASTATE_START = 1;

diff --git a/sc/rtl/riscv_soc.h b/sc/rtl/riscv_soc.h
@@ -111,20 +111,20 @@ SC_MODULE(riscv_soc) {
     bool async_reset_;
     int sim_uart_speedup_rate_;
 
-    
+
     // Hardware SoC Identificator.
     // Read Only unique platform identificator that could be read by FW
     static const uint32_t SOC_HW_ID = 0x20220903;
-    
+
     // UARTx fifo log2(size) in bytes:
     static const int SOC_UART1_LOG2_FIFOSZ = 4;
-    
+
     // Number of available generic IO pins:
     static const int SOC_GPIO0_WIDTH = 12;
-    
+
     // SD-card in SPI mode buffer size. It should be at least log2(512) Bytes:
     static const int SOC_SPI0_LOG2_FIFOSZ = 9;
-    
+
     // Number of contexts in PLIC controller.
     // Example FU740: S7 Core0 (M) + 4xU74 Cores (M+S).
     static const int SOC_PLIC_CONTEXT_TOTAL = 9;

diff --git a/sc/rtl/riverlib/cache/dcache_lru.h b/sc/rtl/riverlib/cache/dcache_lru.h
@@ -91,7 +91,7 @@ SC_MODULE(DCacheLru) {
     static const int lnbits = CFG_LOG2_L1CACHE_BYTES_PER_LINE;
     static const int flbits = DTAG_FL_TOTAL;
     static const int ways = (1 << CFG_DLOG2_NWAYS);
-    
+
     // State machine states:
     static const uint8_t State_Idle = 0;
     static const uint8_t State_CheckHit = 1;
@@ -107,7 +107,7 @@ SC_MODULE(DCacheLru) {
     static const uint8_t State_ResetWrite = 11;
     static const uint8_t State_SnoopSetupAddr = 12;
     static const uint8_t State_SnoopReadData = 13;
-    
+
     static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_L1CACHE_BYTES_PER_LINE) - 1);
     static const uint32_t FLUSH_ALL_VALUE = ((1 << (CFG_DLOG2_LINES_PER_WAY + CFG_DLOG2_NWAYS)) - 1);
 

diff --git a/sc/rtl/riverlib/cache/icache_lru.h b/sc/rtl/riverlib/cache/icache_lru.h
@@ -72,7 +72,7 @@ SC_MODULE(ICacheLru) {
     static const int lnbits = CFG_LOG2_L1CACHE_BYTES_PER_LINE;
     static const int flbits = ITAG_FL_TOTAL;
     static const int ways = (1 << CFG_ILOG2_NWAYS);
-    
+
     // State machine states:
     static const uint8_t State_Idle = 0;
     static const uint8_t State_CheckHit = 1;
@@ -85,7 +85,7 @@ SC_MODULE(ICacheLru) {
     static const uint8_t State_FlushCheck = 9;
     static const uint8_t State_Reset = 10;
     static const uint8_t State_ResetWrite = 11;
-    
+
     static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_L1CACHE_BYTES_PER_LINE) - 1);
     static const uint32_t FLUSH_ALL_VALUE = ((1 << (CFG_ILOG2_LINES_PER_WAY + CFG_ILOG2_NWAYS)) - 1);
 

diff --git a/sc/rtl/riverlib/core/csr.h b/sc/rtl/riverlib/core/csr.h
@@ -49,7 +49,7 @@ SC_MODULE(CsrRegs) {
     sc_in<bool> i_flushd_end;
     sc_in<sc_uint<64>> i_mtimer;                            // Read-only shadow value of memory-mapped mtimer register (see CLINT).
     sc_out<sc_uint<64>> o_executed_cnt;                     // Number of executed instructions
-    
+
     sc_out<bool> o_step;                                    // Stepping enabled
     sc_in<bool> i_dbg_progbuf_ena;                          // Executing progbuf is in progress
     sc_out<bool> o_progbuf_end;                             // End of execution from prog buffer
@@ -59,14 +59,14 @@ SC_MODULE(CsrRegs) {
     sc_out<bool> o_flushmmu_valid;                          // clear specific leaf entry in MMU
     sc_out<bool> o_flushpipeline_valid;                     // flush pipeline, must be don for fence.VMA and fence.i
     sc_out<sc_uint<RISCV_ARCH>> o_flush_addr;               // Cache address to flush. All ones means flush all.
-    
+
     sc_out<bool> o_pmp_ena;                                 // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
     sc_out<bool> o_pmp_we;                                  // write enable into PMP
     sc_out<sc_uint<CFG_PMP_TBL_WIDTH>> o_pmp_region;        // selected PMP region
     sc_out<sc_uint<RISCV_ARCH>> o_pmp_start_addr;           // PMP region start address
     sc_out<sc_uint<RISCV_ARCH>> o_pmp_end_addr;             // PMP region end address (inclusive)
     sc_out<sc_uint<CFG_PMP_FL_TOTAL>> o_pmp_flags;          // {ena, lock, r, w, x}
-    
+
     sc_out<bool> o_mmu_ena;                                 // MMU enabled in U and S modes. Sv48 only.
     sc_out<bool> o_mmu_sv39;                                // Translation mode sv39 is active
     sc_out<bool> o_mmu_sv48;                                // Translation mode sv48 is active
@@ -102,14 +102,14 @@ SC_MODULE(CsrRegs) {
     static const uint32_t State_Fence = 9;
     static const uint32_t State_WaitPmp = 10;
     static const uint32_t State_Response = 11;
-    
+
     static const uint8_t Fence_None = 0;
     static const uint8_t Fence_DataBarrier = 1;
     static const uint8_t Fence_DataFlush = 2;
     static const uint8_t Fence_WaitDataFlushEnd = 3;
     static const uint8_t Fence_FlushInstr = 4;
     static const uint8_t Fence_End = 7;
-    
+
     static const uint8_t SATP_MODE_SV39 = 8;
     static const uint8_t SATP_MODE_SV48 = 9;
 

diff --git a/sc/rtl/riverlib/core/execute.h b/sc/rtl/riverlib/core/execute.h
@@ -141,7 +141,7 @@ SC_MODULE(InstrExecute) {
     static const int Res_IDiv = 9;
     static const int Res_FPU = 10;
     static const int Res_Total = 11;
-    
+
     static const uint8_t State_Idle = 0;
     static const uint8_t State_WaitMemAcces = 1;
     static const uint8_t State_WaitMulti = 2;
@@ -151,11 +151,11 @@ SC_MODULE(InstrExecute) {
     static const uint8_t State_DebugMemRequest = 8;
     static const uint8_t State_DebugMemError = 9;
     static const uint8_t State_Wfi = 0xf;
-    
+
     static const uint8_t CsrState_Idle = 0;
     static const uint8_t CsrState_Req = 1;
     static const uint8_t CsrState_Resp = 2;
-    
+
     static const uint8_t AmoState_WaitMemAccess = 0;
     static const uint8_t AmoState_Read = 1;
     static const uint8_t AmoState_Modify = 2;

diff --git a/sc/rtl/riverlib/core/proc.h b/sc/rtl/riverlib/core/proc.h
@@ -322,6 +322,7 @@ SC_MODULE(Processor) {
     CsrType csr;
     DebugType dbg;
     BranchPredictorType bp;
+
     // csr bridge to executor unit
     sc_signal<bool> iccsr_m0_req_ready;
     sc_signal<bool> iccsr_m0_resp_valid;
@@ -339,6 +340,7 @@ SC_MODULE(Processor) {
     sc_signal<sc_uint<RISCV_ARCH>> iccsr_s0_req_data;
     sc_signal<bool> iccsr_s0_resp_ready;
     sc_signal<bool> iccsr_s0_resp_exception;
+
     sc_signal<bool> w_mem_resp_error;
     sc_signal<bool> w_writeback_ready;
     sc_signal<bool> w_reg_wena;

diff --git a/sc/rtl/riverlib/dmi/dmidebug.cpp b/sc/rtl/riverlib/dmi/dmidebug.cpp
@@ -58,8 +58,8 @@ dmidebug::dmidebug(sc_module_name name,
     tap = 0;
 
     tap = new jtagtap<7,
-                      5>("tap",
-                         CFG_DMI_TAP_ID);
+                      5,
+                      CFG_DMI_TAP_ID>("tap");
     tap->i_trst(i_trst);
     tap->i_tck(i_tck);
     tap->i_tms(i_tms);

diff --git a/sc/rtl/riverlib/dmi/dmidebug.h b/sc/rtl/riverlib/dmi/dmidebug.h
@@ -198,7 +198,7 @@ SC_MODULE(dmidebug) {
     sc_signal<bool> w_jtag_dmi_error;
 
     jtagcdc *cdc;
-    jtagtap<7, 5> *tap;
+    jtagtap<7, 5, CFG_DMI_TAP_ID> *tap;
 
 };
 

diff --git a/sc/rtl/riverlib/dmi/jtagtap.h b/sc/rtl/riverlib/dmi/jtagtap.h
@@ -21,7 +21,8 @@
 namespace debugger {
 
 template<int abits = 7,
-         int irlen = 5>
+         int irlen = 5,
+         uint32_t idcode = 0x10e31913>
 SC_MODULE(jtagtap) {
  public:
     sc_in<bool> i_trst;                                     // Must be open-train, pullup
@@ -44,30 +45,27 @@ SC_MODULE(jtagtap) {
 
     SC_HAS_PROCESS(jtagtap);
 
-    jtagtap(sc_module_name name,
-            sc_uint<32> idcode);
+    jtagtap(sc_module_name name);
 
     void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
 
  private:
-    sc_uint<32> idcode_;
-
     static const int drlen = ((abits + 32) + 2);
-    
+
     static const uint8_t IR_IDCODE = 0x01;
     static const uint8_t IR_DTMCONTROL = 0x10;
     static const uint8_t IR_DBUS = 0x11;
     static const uint8_t IR_BYPASS = 0x1f;
-    
+
     static const uint8_t DMISTAT_SUCCESS = 0x0;
     static const uint8_t DMISTAT_RESERVED = 0x1;
     static const uint8_t DMISTAT_FAILED = 0x2;
     static const uint8_t DMISTAT_BUSY = 0x3;
-    
+
     // DTMCONTROL register bits
     static const int DTMCONTROL_DMIRESET = 16;
     static const int DTMCONTROL_DMIHARDRESET = 17;
-    
+
     // JTAG states:
     static const uint8_t RESET_TAP = 0;
     static const uint8_t IDLE = 1;
@@ -99,7 +97,7 @@ SC_MODULE(jtagtap) {
     void jtagtap_r_reset(jtagtap_registers &iv) {
         iv.state = RESET_TAP;
         iv.dr_length = 0;
-        iv.dr = idcode_;
+        iv.dr = idcode;
         iv.bypass = 0;
         iv.datacnt = 0;
         iv.dmi_busy = 0;
@@ -118,9 +116,8 @@ SC_MODULE(jtagtap) {
 
 };
 
-template<int abits, int irlen>
-jtagtap<abits, irlen>::jtagtap(sc_module_name name,
-                               sc_uint<32> idcode)
+template<int abits, int irlen, uint32_t idcode>
+jtagtap<abits, irlen, idcode>::jtagtap(sc_module_name name)
     : sc_module(name),
     i_trst("i_trst"),
     i_tck("i_tck"),
@@ -136,7 +133,6 @@ jtagtap<abits, irlen>::jtagtap(sc_module_name name,
     i_dmi_error("i_dmi_error"),
     o_dmi_hardreset("o_dmi_hardreset") {
 
-    idcode_ = idcode;
 
     SC_METHOD(comb);
     sensitive << i_trst;
@@ -165,8 +161,8 @@ jtagtap<abits, irlen>::jtagtap(sc_module_name name,
     sensitive << i_tck.neg();
 }
 
-template<int abits, int irlen>
-void jtagtap<abits, irlen>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
+template<int abits, int irlen, uint32_t idcode>
+void jtagtap<abits, irlen, idcode>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
     std::string pn(name());
     if (o_vcd) {
         sc_trace(o_vcd, i_trst, i_trst.name());
@@ -195,8 +191,8 @@ void jtagtap<abits, irlen>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_v
 
 }
 
-template<int abits, int irlen>
-void jtagtap<abits, irlen>::comb() {
+template<int abits, int irlen, uint32_t idcode>
+void jtagtap<abits, irlen, idcode>::comb() {
     sc_uint<drlen> vb_dr;
     bool v_dmi_req_valid;
     bool v_dmi_req_write;
@@ -249,7 +245,7 @@ void jtagtap<abits, irlen>::comb() {
             v.state = SHIFT_DR;
         }
         if (nr.ir.read() == IR_IDCODE) {
-            vb_dr = idcode_;
+            vb_dr = idcode;
             v.dr_length = 32;
         } else if (nr.ir.read() == IR_DTMCONTROL) {
             vb_dr(31, 0) = 0;
@@ -406,17 +402,17 @@ void jtagtap<abits, irlen>::comb() {
     o_dmi_hardreset = v_dmi_hardreset;
 }
 
-template<int abits, int irlen>
-void jtagtap<abits, irlen>::registers() {
+template<int abits, int irlen, uint32_t idcode>
+void jtagtap<abits, irlen, idcode>::registers() {
     if (i_trst.read() == 1) {
         jtagtap_r_reset(r);
     } else {
         r = v;
     }
 }
 
-template<int abits, int irlen>
-void jtagtap<abits, irlen>::nregisters() {
+template<int abits, int irlen, uint32_t idcode>
+void jtagtap<abits, irlen, idcode>::nregisters() {
     if (i_trst.read() == 1) {
         jtagtap_nr_reset(nr);
     } else {

diff --git a/sc/rtl/riverlib/l2cache/l2_top.h b/sc/rtl/riverlib/l2cache/l2_top.h
@@ -54,6 +54,7 @@ SC_MODULE(L2Top) {
     sc_signal<sc_uint<3>> wb_req_prot;
     sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_req_wdata;
     sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> wb_req_wstrb;
+
     sc_signal<bool> w_cache_valid;
     sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_cache_rdata;
     sc_signal<sc_uint<2>> wb_cache_status;

diff --git a/sc/rtl/riverlib/l2cache/l2cache_lru.h b/sc/rtl/riverlib/l2cache/l2cache_lru.h
@@ -74,7 +74,7 @@ SC_MODULE(L2CacheLru) {
     static const int lnbits = CFG_L2_LOG2_BYTES_PER_LINE;
     static const int flbits = L2TAG_FL_TOTAL;
     static const int ways = (1 << CFG_L2_LOG2_NWAYS);
-    
+
     // State machine states:
     static const uint8_t State_Idle = 0;
     static const uint8_t State_CheckHit = 1;
@@ -88,7 +88,7 @@ SC_MODULE(L2CacheLru) {
     static const uint8_t State_FlushCheck = 9;
     static const uint8_t State_Reset = 10;
     static const uint8_t State_ResetWrite = 11;
-    
+
     static const uint64_t LINE_BYTES_MASK = ((1 << CFG_L2_LOG2_BYTES_PER_LINE) - 1);
     static const uint32_t FLUSH_ALL_VALUE = ((1 << (CFG_L2_LOG2_LINES_PER_WAY + CFG_L2_LOG2_NWAYS)) - 1);
 

diff --git a/sc/rtl/sdctrl/sdctrl.h b/sc/rtl/sdctrl/sdctrl.h
@@ -146,6 +146,7 @@ SC_MODULE(sdctrl) {
     sc_signal<bool> w_wdog_trigger;
     sc_signal<sc_uint<4>> wb_err_code;
     sc_signal<bool> w_err_pending;
+
     // SPI-mode controller signals:
     sc_signal<bool> w_spi_dat;
     sc_signal<bool> w_spi_dat_csn;
@@ -164,6 +165,7 @@ SC_MODULE(sdctrl) {
     sc_signal<bool> w_spi_wdog_ena;
     sc_signal<bool> w_spi_crc16_clear;
     sc_signal<bool> w_spi_crc16_next;
+
     // SD-mode controller signals:
     sc_signal<bool> w_sd_dat0;
     sc_signal<bool> w_sd_dat0_dir;
@@ -188,6 +190,7 @@ SC_MODULE(sdctrl) {
     sc_signal<bool> w_sd_wdog_ena;
     sc_signal<bool> w_sd_crc16_clear;
     sc_signal<bool> w_sd_crc16_next;
+
     // Mode multiplexed signals:
     sc_signal<bool> w_cmd_req_valid;
     sc_signal<sc_uint<6>> wb_cmd_req_cmd;

diff --git a/sc/rtl/sdctrl/sdctrl_cache.h b/sc/rtl/sdctrl/sdctrl_cache.h
@@ -68,7 +68,7 @@ SC_MODULE(sdctrl_cache) {
     static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
     static const int lnbits = CFG_LOG2_SDCACHE_BYTES_PER_LINE;
     static const int flbits = SDCACHE_FL_TOTAL;
-    
+
     // State machine states:
     static const uint8_t State_Idle = 0;
     static const uint8_t State_CheckHit = 2;
@@ -82,7 +82,7 @@ SC_MODULE(sdctrl_cache) {
     static const uint8_t State_FlushCheck = 9;
     static const uint8_t State_Reset = 10;
     static const uint8_t State_ResetWrite = 11;
-    
+
     static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
 
     struct sdctrl_cache_registers {

diff --git a/sv/rtl/riverlib/core/csr.sv b/sv/rtl/riverlib/core/csr.sv
@@ -48,7 +48,7 @@ module CsrRegs #(
     input logic i_flushd_end,
     input logic [63:0] i_mtimer,                            // Read-only shadow value of memory-mapped mtimer register (see CLINT).
     output logic [63:0] o_executed_cnt,                     // Number of executed instructions
-    
+
     output logic o_step,                                    // Stepping enabled
     input logic i_dbg_progbuf_ena,                          // Executing progbuf is in progress
     output logic o_progbuf_end,                             // End of execution from prog buffer
@@ -58,14 +58,14 @@ module CsrRegs #(
     output logic o_flushmmu_valid,                          // clear specific leaf entry in MMU
     output logic o_flushpipeline_valid,                     // flush pipeline, must be don for fence.VMA and fence.i
     output logic [river_cfg_pkg::RISCV_ARCH-1:0] o_flush_addr,// Cache address to flush. All ones means flush all.
-    
+
     output logic o_pmp_ena,                                 // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
     output logic o_pmp_we,                                  // write enable into PMP
     output logic [river_cfg_pkg::CFG_PMP_TBL_WIDTH-1:0] o_pmp_region,// selected PMP region
     output logic [river_cfg_pkg::RISCV_ARCH-1:0] o_pmp_start_addr,// PMP region start address
     output logic [river_cfg_pkg::RISCV_ARCH-1:0] o_pmp_end_addr,// PMP region end address (inclusive)
     output logic [river_cfg_pkg::CFG_PMP_FL_TOTAL-1:0] o_pmp_flags,// {ena, lock, r, w, x}
-    
+
     output logic o_mmu_ena,                                 // MMU enabled in U and S modes. Sv48 only.
     output logic o_mmu_sv39,                                // Translation mode sv39 is active
     output logic o_mmu_sv48,                                // Translation mode sv48 is active