[!] Fix verilog build errors. Run asic_sim successfully

sergeykhbr · Dec 10, 2023 · ac92e5b · ac92e5b
1 parent 0a8ed6d
commit ac92e5b
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Showing 3 changed files with 4 additions and 2 deletions.
diff --git a/sv/rtl/riscv_soc.sv b/sv/rtl/riscv_soc.sv
@@ -76,6 +76,7 @@ module riscv_soc #(
     input types_amba_pkg::axi4_slave_out_type i_ddr_xslvo   // AXI DDR memory interface
 );
 
+import target_cfg_pkg::*;
 import types_amba_pkg::*;
 import types_pnp_pkg::*;
 import types_bus0_pkg::*;

diff --git a/sv/rtl/riverlib/core/tracer.sv b/sv/rtl/riverlib/core/tracer.sv
@@ -894,7 +894,8 @@ initial begin
     assert (fl)
     else begin
         $warning("Cannot open log-file");
-    endend
+    end
+end
 
 always_comb
 begin: comb_proc

diff --git a/sv/rtl/riverlib/core/tracer_pkg.sv b/sv/rtl/riverlib/core/tracer_pkg.sv
@@ -19,7 +19,7 @@ import river_cfg_pkg::*;
 
 localparam int TRACE_TBL_ABITS = 6;
 localparam int TRACE_TBL_SZ = 64;
-localparam rname[0:64-1] = '{
+localparam string rname[0:64-1] = '{
     "zero",  // x0
     "ra",  // x1
     "sp",  // x2