[*] regenerate system verilog with the new version of rtlgen generator

sergeykhbr · Dec 10, 2023 · f179595 · f179595
1 parent b3ee236
commit f179595
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Showing 113 changed files with 214 additions and 492 deletions.
diff --git a/sv/prj/common/vips/clk/vip_clk.sv b/sv/prj/common/vips/clk/vip_clk.sv
@@ -17,7 +17,7 @@
 `timescale 1ns/10ps
 
 module vip_clk #(
-    parameter realtime period = 1
+    parameter realtime period = 1.0
 )
 (
     output logic o_clk
@@ -28,7 +28,7 @@ import vip_clk_pkg::*;
 logic pll;
 
 initial begin
-    pll = 1'b0;
+    pll = 0;
 end
 always begin
     #(0.5 * 1000000000 * period) pll = ~pll;

diff --git a/sv/prj/common/vips/sdcard/vip_sdcard_cmdio.sv b/sv/prj/common/vips/sdcard/vip_sdcard_cmdio.sv
@@ -187,7 +187,7 @@ begin: comb_proc
                 vb_cmd_txshift = 48'd0;
                 vb_cmd_txshift[45: 40] = r.cmd_rxshift[45: 40];
                 vb_cmd_txshift[39: 8] = i_cmd_resp_data32;
-                vb_cmd_txshift[7: 0] = 8'hff;
+                vb_cmd_txshift[7: 0] = 8'hFF;
             end else begin
                 // Default R1 response in SPI mode:
                 v.bitcnt = 6'd7;
@@ -294,7 +294,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/prj/common/vips/sdcard/vip_sdcard_crc7.sv b/sv/prj/common/vips/sdcard/vip_sdcard_crc7.sv
@@ -84,7 +84,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/prj/common/vips/sdcard/vip_sdcard_ctrl.sv b/sv/prj/common/vips/sdcard/vip_sdcard_ctrl.sv
@@ -23,7 +23,7 @@ module vip_sdcard_ctrl #(
     parameter logic [3:0] CFG_SDCARD_VHS = 4'h1,            // CMD8 Voltage supply mask
     parameter logic CFG_SDCARD_PCIE_1_2V = 1'b0,
     parameter logic CFG_SDCARD_PCIE_AVAIL = 1'b0,
-    parameter logic [23:0] CFG_SDCARD_VDD_VOLTAGE_WINDOW = 24'hff8000
+    parameter logic [23:0] CFG_SDCARD_VDD_VOLTAGE_WINDOW = 24'hFF8000
 )
 (
     input logic i_nrst,
@@ -241,7 +241,7 @@ begin: comb_proc
         if ((r.req_mem_valid == 1'b1) && (i_cmdio_busy == 1'b0) && (i_cs == 1'b0)) begin
             v.req_mem_valid = 1'b0;
             v.datastate = DATASTATE_START;
-            v.shiftdat = 16'hfe00;
+            v.shiftdat = 16'hFE00;
             v.bitcnt = 13'd0;
             v.dat_trans = 1'b1;
         end
@@ -315,7 +315,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/prj/common/vips/sdcard/vip_sdcard_top.sv b/sv/prj/common/vips/sdcard/vip_sdcard_top.sv
@@ -246,8 +246,8 @@ begin: comb_proc
     w_stat_wp_violation = 1'b0;
     w_stat_erase_param = 1'b0;
     w_stat_out_of_range = 1'b0;
-    wb_mem_rdata = 8'hff;
-    wb_crc16 = 16'h7fa1;
+    wb_mem_rdata = 8'hFF;
+    wb_crc16 = 16'h7FA1;
 end: comb_proc
 
 endmodule: vip_sdcard_top
diff --git a/sv/prj/common/vips/sdcard/vip_sdcard_top_pkg.sv b/sv/prj/common/vips/sdcard/vip_sdcard_top_pkg.sv
@@ -22,6 +22,6 @@ localparam bit CFG_SDCARD_HCS = 1'b1;                       // High Capacity Sup
 localparam bit [3:0] CFG_SDCARD_VHS = 4'h1;                 // CMD8 Voltage supply mask
 localparam bit CFG_SDCARD_PCIE_1_2V = 1'b0;
 localparam bit CFG_SDCARD_PCIE_AVAIL = 1'b0;
-localparam bit [23:0] CFG_SDCARD_VDD_VOLTAGE_WINDOW = 24'hff8000;
+localparam bit [23:0] CFG_SDCARD_VDD_VOLTAGE_WINDOW = 24'hFF8000;
 
 endpackage: vip_sdcard_top_pkg
diff --git a/sv/prj/common/vips/spi/vip_spi_top.sv b/sv/prj/common/vips/spi/vip_spi_top.sv
@@ -95,7 +95,7 @@ begin: comb_proc
 
     case (wb_req_addr[7: 2])
     6'h00: begin                                            // [0x00] hwid
-        rdata = 32'hcafecafe;
+        rdata = 32'hCAFECAFE;
     end
     6'h01: begin                                            // [0x04] scratch0
         rdata = r.scratch0;
@@ -162,7 +162,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/prj/common/vips/spi/vip_spi_transmitter.sv b/sv/prj/common/vips/spi/vip_spi_transmitter.sv
@@ -149,7 +149,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/prj/impl/asic/asic_top_pkg.sv b/sv/prj/impl/asic/asic_top_pkg.sv
@@ -15,6 +15,9 @@
 // 
 package asic_top_pkg;
 
+import types_amba_pkg::*;
+import types_pnp_pkg::*;
+
 localparam bit async_reset = 0;
 
 endpackage: asic_top_pkg
diff --git a/sv/rtl/ambalib/apb_slv.sv b/sv/rtl/ambalib/apb_slv.sv
@@ -130,7 +130,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/rtl/ambalib/axi2apb_bus1.sv b/sv/rtl/ambalib/axi2apb_bus1.sv
@@ -201,7 +201,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/rtl/ambalib/axi_slv.sv b/sv/rtl/ambalib/axi_slv.sv
@@ -262,7 +262,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/rtl/ambalib/axi_slv_pkg.sv b/sv/rtl/ambalib/axi_slv_pkg.sv
@@ -56,7 +56,7 @@ const axi_slv_registers axi_slv_r_reset = '{
     '0,                                 // req_wstrb
     '0,                                 // req_xsize
     '0,                                 // req_len
-    1'b0,                               // req_user
+    '0,                                 // req_user
     '0,                                 // req_id
     '0,                                 // req_burst
     1'b0,                               // req_last_a

diff --git a/sv/rtl/ambalib/axictrl_bus0.sv b/sv/rtl/ambalib/axictrl_bus0.sv
@@ -299,7 +299,6 @@ generate
             end
         end: rg_proc
 
-
     end: async_rst_gen
     else begin: no_rst_gen
 

diff --git a/sv/rtl/ambalib/types_amba_pkg.sv b/sv/rtl/ambalib/types_amba_pkg.sv
@@ -33,10 +33,7 @@ typedef struct {
 } mapinfo_type;
 
 // @brief Empty entry value for the map info table
-const mapinfo_type mapinfo_none = '{
-    '0,  // addr_start
-    '0  // addr_end
-};
+const mapinfo_type mapinfo_none = '{0, 0};
 
 // Burst length size decoder
 localparam int XSIZE_TOTAL = 8;
@@ -85,10 +82,10 @@ localparam bit [1:0] AXI_BURST_WRAP = 2'd2;
 // @}
 
 localparam bit [3:0] ARCACHE_DEVICE_NON_BUFFERABLE = 4'h0;
-localparam bit [3:0] ARCACHE_WRBACK_READ_ALLOCATE = 4'hf;
+localparam bit [3:0] ARCACHE_WRBACK_READ_ALLOCATE = 4'hF;
 
 localparam bit [3:0] AWCACHE_DEVICE_NON_BUFFERABLE = 4'h0;
-localparam bit [3:0] AWCACHE_WRBACK_WRITE_ALLOCATE = 4'hf;
+localparam bit [3:0] AWCACHE_WRBACK_WRITE_ALLOCATE = 4'hF;
 
 // see table C3-7 Permitted read address control signal combinations
 //  
@@ -98,7 +95,7 @@ localparam bit [3:0] AWCACHE_WRBACK_WRITE_ALLOCATE = 4'hf;
 //     0    |    1     |    1     |    ReadMakeUnique
 localparam bit [3:0] ARSNOOP_READ_NO_SNOOP = 4'h0;
 localparam bit [3:0] ARSNOOP_READ_SHARED = 4'h1;
-localparam bit [3:0] ARSNOOP_READ_MAKE_UNIQUE = 4'hc;
+localparam bit [3:0] ARSNOOP_READ_MAKE_UNIQUE = 4'hC;
 
 // see table C3-8 Permitted read address control signal combinations
 //  
@@ -112,7 +109,7 @@ localparam bit [2:0] AWSNOOP_WRITE_BACK = 3'h3;
 
 // see table C3-19
 localparam bit [3:0] AC_SNOOP_READ_UNIQUE = 4'h7;
-localparam bit [3:0] AC_SNOOP_MAKE_INVALID = 4'hd;
+localparam bit [3:0] AC_SNOOP_MAKE_INVALID = 4'hD;
 
 typedef struct {
     logic [CFG_SYSBUS_ADDR_BITS-1:0] addr;
@@ -167,17 +164,7 @@ typedef struct {
     logic [3:0] region;
 } axi4_metadata_type;
 
-const axi4_metadata_type META_NONE = '{
-    '0,  // addr
-    '0,  // len
-    '0,  // size
-    AXI_BURST_INCR,  // burst
-    1'b0,  // lock
-    '0,  // cache
-    '0,  // prot
-    '0,  // qos
-    '0  // region
-};
+const axi4_metadata_type META_NONE = '{'0, '0, '0, AXI_BURST_INCR, 1'b0, '0, '0, '0, '0};
 
 
 typedef struct {
@@ -201,23 +188,7 @@ typedef struct {
 // @brief   Master device empty value.
 // @warning If the master is not connected to the vector begin vector value
 //          MUST BE initialized by this value.
-const axi4_master_out_type axi4_master_out_none = '{
-    1'b0,  // aw_valid
-    META_NONE,  // aw_bits
-    '0,  // aw_id
-    1'b0,  // aw_user
-    1'b0,  // w_valid
-    '0,  // w_data
-    1'b0,  // w_last
-    '0,  // w_strb
-    1'b0,  // w_user
-    1'b0,  // b_ready
-    1'b0,  // ar_valid
-    META_NONE,  // ar_bits
-    '0,  // ar_id
-    1'b0,  // ar_user
-    1'b0  // r_ready
-};
+const axi4_master_out_type axi4_master_out_none = '{1'b0, META_NONE, '0, '0, 1'b0, '0, 1'b0, '0, '0, 1'b0, 1'b0, META_NONE, '0, '0, 1'b0};
 
 // @brief Master device input signals.
 typedef struct {
@@ -236,21 +207,7 @@ typedef struct {
     logic [CFG_SYSBUS_USER_BITS-1:0] r_user;
 } axi4_master_in_type;
 
-const axi4_master_in_type axi4_master_in_none = '{
-    1'b0,  // aw_ready
-    1'b0,  // w_ready
-    1'b0,  // b_valid
-    '0,  // b_resp
-    '0,  // b_id
-    1'b0,  // b_user
-    1'b0,  // ar_ready
-    1'b0,  // r_valid
-    '0,  // r_resp
-    '0,  // r_data
-    1'b0,  // r_last
-    '0,  // r_id
-    1'b0  // r_user
-};
+const axi4_master_in_type axi4_master_in_none = '{1'b0, 1'b0, 1'b0, '0, '0, '0, 1'b0, 1'b0, '0, '0, 1'b0, '0, '0};
 
 
 typedef struct {
@@ -271,23 +228,7 @@ typedef struct {
     logic r_ready;
 } axi4_slave_in_type;
 
-const axi4_slave_in_type axi4_slave_in_none = '{
-    1'b0,  // aw_valid
-    META_NONE,  // aw_bits
-    '0,  // aw_id
-    1'b0,  // aw_user
-    1'b0,  // w_valid
-    '0,  // w_data
-    1'b0,  // w_last
-    '0,  // w_strb
-    1'b0,  // w_user
-    1'b0,  // b_ready
-    1'b0,  // ar_valid
-    META_NONE,  // ar_bits
-    '0,  // ar_id
-    1'b0,  // ar_user
-    1'b0  // r_ready
-};
+const axi4_slave_in_type axi4_slave_in_none = '{1'b0, META_NONE, '0, '0, 1'b0, '0, 1'b0, '0, '0, 1'b0, 1'b0, META_NONE, '0, '0, 1'b0};
 
 typedef struct {
     logic aw_ready;
@@ -305,21 +246,7 @@ typedef struct {
     logic [CFG_SYSBUS_USER_BITS-1:0] r_user;
 } axi4_slave_out_type;
 
-const axi4_slave_out_type axi4_slave_out_none = '{
-    1'b0,  // aw_ready
-    1'b0,  // w_ready
-    1'b0,  // b_valid
-    '0,  // b_resp
-    '0,  // b_id
-    1'b0,  // b_user
-    1'b0,  // ar_ready
-    1'b0,  // r_valid
-    '0,  // r_resp
-    '0,  // r_data
-    1'b0,  // r_last
-    '0,  // r_id
-    1'b0  // r_user
-};
+const axi4_slave_out_type axi4_slave_out_none = '{1'b0, 1'b0, 1'b0, '0, '0, '0, 1'b0, 1'b0, '0, '0, 1'b0, '0, '0};
 
 
 typedef struct {
@@ -332,26 +259,14 @@ typedef struct {
     logic [3:0] pstrb;
 } apb_in_type;
 
-const apb_in_type apb_in_none = '{
-    '0,  // paddr
-    '0,  // pprot
-    1'b0,  // pselx
-    1'b0,  // penable
-    1'b0,  // pwrite
-    '0,  // pwdata
-    '0  // pstrb
-};
+const apb_in_type apb_in_none = '{'0, '0, 1'b0, 1'b0, 1'b0, '0, '0};
 
 typedef struct {
     logic pready;                                           // when 1 it breaks callback to functional model
     logic [31:0] prdata;
     logic pslverr;
 } apb_out_type;
 
-const apb_out_type apb_out_none = '{
-    1'b0,  // pready
-    '0,  // prdata
-    1'b0  // pslverr
-};
+const apb_out_type apb_out_none = '{1'b0, '0, 1'b0};
 
 endpackage: types_amba_pkg
diff --git a/sv/rtl/ambalib/types_bus0_pkg.sv b/sv/rtl/ambalib/types_bus0_pkg.sv
@@ -67,9 +67,9 @@ const bus0_mapinfo_vector CFG_BUS0_MAP = '{
     '{64'h0000000000010000, 64'h0000000000050000},          // 0, bootrom, 256 KB
     '{64'h0000000002000000, 64'h0000000002010000},          // 1, clint
     '{64'h0000000008000000, 64'h0000000008200000},          // 2, sram, 2MB
-    '{64'h000000000c000000, 64'h0000000010000000},          // 3, plic
+    '{64'h000000000C000000, 64'h0000000010000000},          // 3, plic
     '{64'h0000000010000000, 64'h0000000010100000},          // 4, APB bridge: uart1
-    '{64'h0000000080000000, 64'h00000000c0000000},          // 5, ddr, 512 MB
+    '{64'h0000000080000000, 64'h00000000C0000000},          // 5, ddr, 512 MB
     '{64'h0000000800000000, 64'h0000001000000000}           // 6, sdctrl, 32 GB
 };
 

diff --git a/sv/rtl/ambalib/types_bus1_pkg.sv b/sv/rtl/ambalib/types_bus1_pkg.sv
@@ -49,11 +49,11 @@ typedef mapinfo_type bus1_mapinfo_vector[0:CFG_BUS1_PSLV_TOTAL - 1];
 const bus1_mapinfo_vector CFG_BUS1_MAP = '{
     '{64'h0000000000010000, 64'h0000000000011000},          // 0, uart1 4KB
     '{64'h0000000000012000, 64'h0000000000013000},          // 1, PRCI 4KB
-    '{64'h000000000001e000, 64'h000000000001f000},          // 2, dmi 4KB. TODO: change base address
+    '{64'h000000000001E000, 64'h000000000001F000},          // 2, dmi 4KB. TODO: change base address
     '{64'h0000000000050000, 64'h0000000000051000},          // 4, SPI SD-card 4KB
     '{64'h0000000000060000, 64'h0000000000061000},          // 3, GPIO 4KB
-    '{64'h00000000000c0000, 64'h00000000000c1000},          // 5, DDR MGMT 4KB
-    '{64'h00000000000ff000, 64'h0000000000100000}           // 6, Plug'n'Play 4KB
+    '{64'h00000000000C0000, 64'h00000000000C1000},          // 5, DDR MGMT 4KB
+    '{64'h00000000000FF000, 64'h0000000000100000}           // 6, Plug'n'Play 4KB
 };
 
 endpackage: types_bus1_pkg