Reset input for Sequence Generator

[eparadis]

It seems that the Sequence Generator once had a reset input (discussion from PR here). Without a reset input, they're very hard to use. Could a reset input be added?

I have been noodling with bit-serial CPU designs and the ability to insert arbitrary bit sequences at different points of the circuit would greatly simplify things. Right now I have to "build one from scratch" with all the complexity and limitations that entails.

For anyone else looking for a work around in the mean time, I have found that short sequence generators can be created using Custom Logic blocks. Here is an example for a 4-bit sequence.

Inputs: Clk, Rst, D0, D1, D2, D3
Output: DO, S0, S1, S2, S3
Definition:
10A??? 00000=A1000
?1A??? ?????=A1000
+0ABCD ?1000=B0100
+0ABCD ?0100=C0010
+0ABCD ?0010=D0001
+0ABCD ?0001=A1000

I modeled the behavior after the timing diagrams of the T.I. CD54HC4017. When RESET goes high, the sequence output is held at the first step.

[kubark42]

@eparadis thanks, this is brilliant. I agree that the sequence generator should have a reset-- and ideally an initial state as well, but your workaround got me on the right path.