Branch "block1" (i.e., the Block I AGC and DSKY simulations) merged into

master (making the block1 branch obsolete).  The VirtualAGC GUI now runs
Solarium 55 (i.e., the Block I AGC code), using either the control-panel
or nav-bay DSKY styles, as well as Sunburst 120 (Apollo 5) and Aurora
12.

Makefile

@@ -144,6 +144,7 @@
 #				mission sources using yaYUL.
 #		2016-10-21 RSB	Added AURORA12 to the missions.
 #		2016-11-03 RSB	Added SUNBURST120 to the missions.
+#		2016-11-08 RSB	Merged in block1 branch.
 #
 # The build box is always Linux for cross-compiles.  For native compiles:
 #	Use "make MACOSX=yes" for Mac OS X.
@@ -153,7 +154,7 @@
 #	Use "make" for Linux.
 
 # NVER is the overall version code for the release.
-NVER:=\\\"2016-08-21-working\\\"
+NVER:=\\\"2016-11-08-working\\\"
 DATE:=`date +%Y%m%d`
 
 # DON'T CHANGE THE FOLLOWING SWITCH *********************************
@@ -288,6 +289,7 @@ export MISSIONS
 
 # The base set of targets to be built always.
 SUBDIRS = Tools yaLEMAP yaAGC yaAGS yaYUL ControlPulseSim yaUniverse
+SUBDIRS += yaAGC-Block1-Pultorak yaAGCb1 yaUplinkBlock1 Validation-Block1
 SUBDIRS += $(MISSIONS)
 
 ifndef NOGUI
@@ -308,6 +310,7 @@ SUBDIRS += yaACA2
 SUBDIRS += yaACA3
 SUBDIRS += yaTelemetry 
 SUBDIRS += jWiz
+SUBDIRS += yaDSKYb1
 SUBDIRS += VirtualAGC
 endif # NOGUI
 
@@ -375,6 +378,9 @@ yaTelemetry:
 jWiz:
 	$(BUILD) -C $@ $(ISMACOSX) $(DEV_STATIC)
 
+yaAGC-Block1-Pultorak yaAGCb1 yaDSKYb1 yaUplinkBlock1 yaValidation-Block1:
+	$(BUILD) -C $@ $(DEV_STATIC)
+
 .PHONY: VirtualAGC
 VirtualAGC:
 	$(BUILD) -C $@ "YADSKY_SUFFIX=$(YADSKY_SUFFIX)" "YADEDA_SUFFIX=$(YADEDA_SUFFIX)" $(ISMACOSX) $(DEV_STATIC)
@@ -469,6 +475,11 @@ clean: clean-missions
 	$(MAKE) -C yaDEDA2 clean
 	$(MAKE) -C yaACA2 clean
 	$(MAKE) -C Tools clean
+	$(MAKE) -C yaAGC-Block1-Pultorak clean
+	$(MAKE) -C yaAGCb1 clean
+	$(MAKE) -C yaDSKYb1 clean
+	$(MAKE) -C yaUplinkBlock1 clean
+	$(MAKE) -C Validation-Block1 clean
 	-rm -f `find . -name "core"` FP6/*.aea.html FP8/*.aea.html
 
 autogen:

Pultorak-Simulator-1.16/ADR.cpp

@@ -0,0 +1,105 @@
+/****************************************************************************
+ * ADR - MEMORY ADDRESS subsystem
+ *
+ * AUTHOR: John Pultorak
+ * DATE: 9/22/01
+ * FILE: ADR.cpp
+ *
+ * NOTES: see header file.
+ *
+ *****************************************************************************
+ */
+#include "reg.h"
+#include "ADR.h"
+#include "SEQ.h"
+#include "BUS.h"
+regS ADR::register_S; // address register
+regBNK ADR::register_BNK; // bank register
+// transfer bits 14-11 from the bus into the 4-bit bank register
+unsigned ADR::conv_WBK[] =
+  { BX, BX, BX, BX, BX, BX, BX, BX, BX, BX, BX, BX, B14, B13, B12, B11 };
+void
+ADR::execWP_WS()
+{
+  register_S.write(BUS::glbl_WRITE_BUS);
+}
+void
+ADR::execRP_RBK()
+{
+  BUS::glbl_READ_BUS = register_BNK.read() << 10;
+}
+void
+ADR::execWP_WBK()
+{
+  register_BNK.writeShift(BUS::glbl_WRITE_BUS, ADR::conv_WBK);
+}
+bool
+ADR::GTR_27()
+{
+  return (register_S.read() > 027);
+}
+bool
+ADR::GTR_17()
+{
+  // check: address is not a central register
+  return (register_S.read() > 017);
+}
+bool
+ADR::EQU_25()
+{
+  return (register_S.read() == 025);
+}
+bool
+ADR::EQU_17()
+{
+// check: instruction is INHINT (INDEX 017)
+  return (register_S.read() == 017);
+}
+bool
+ADR::EQU_16()
+{
+  // check: instruction is RELINT (INDEX 016))
+  return (register_S.read() == 016);
+}
+bool
+ADR::GTR_1777()
+{
+  // check: address is fixed memory
+  return (register_S.read() > 01777);
+}
+unsigned
+ADR::bankDecoder()
+{
+  // Memory is organized into 13 banks of 1K words each. The banks are numbered
+  // 0-12. Bank 0 is erasable memory; banks 1-12 are fixed (rope) memory. The 10
+  // lower bits in the S register address memory inside a bank. The 2 upper bits
+  // in the S register select the bank. If the 2 upper bits are both 1, the 4-bit
+  // bank register is used to select the bank.
+  // 12 11 Bank
+  // 0 0 0 erasable memory
+  // 0 1 1 fixed-fixed 1 memory
+  // 1 0 2 fixed-fixed 2 memory
+  // 1 1 3-12 fixed-switchable memory (bank register selects bank)
+  unsigned bank = ADR::register_S.readField(12, 11);
+  if (bank == 3)
+    {
+      // fixed-switchable
+      if (register_BNK.read() <= 03) // defaults to 6000 - 7777
+        return 03;
+      else
+        return register_BNK.read(); // 10000 - 31777
+    }
+  else
+    return bank; // erasable or fixed-fixed
+}
+unsigned
+ADR::getEffectiveAddress()
+{
+  // Return the 14-bit address selected by lower 10 bits of the S register (1K)
+  // and the bank decoder (which selects the 1K bank)
+  unsigned lowAddress = ADR::register_S.readField(10, 1);
+  if (ADR::bankDecoder() == 0)
+    return lowAddress;
+  unsigned highAddress = ADR::bankDecoder() << 10;
+  return highAddress | lowAddress;
+}

Pultorak-Simulator-1.16/ADR.h

@@ -0,0 +1,104 @@
+/****************************************************************************
+ * ADR - MEMORY ADDRESS subsystem
+ *
+ * AUTHOR: John Pultorak
+ * DATE: 9/22/01
+ * FILE: ADR.h
+ *
+ * VERSIONS:
+ *
+ * DESCRIPTION:
+ * Memory address for the Block 1 Apollo Guidance Computer prototype (AGC4).
+ *
+ * SOURCES:
+ * Mostly based on information from "Logical Description for the Apollo
+ * Guidance Computer (AGC4)", Albert Hopkins, Ramon Alonso, and Hugh
+ * Blair-Smith, R-393, MIT Instrumentation Laboratory, 1963.
+ *
+ * NOTES:
+ *
+ *****************************************************************************
+ */
+#ifndef ADR_H
+#define ADR_H
+enum specialRegister
+{ // octal addresses of special registers
+  // Flip-Flop registers
+  A_ADDR = 00,
+  Q_ADDR = 01,
+  Z_ADDR = 02,
+  LP_ADDR = 03,
+  IN0_ADDR = 04,
+  IN1_ADDR = 05,
+  IN2_ADDR = 06,
+  IN3_ADDR = 07,
+  OUT0_ADDR = 010,
+  OUT1_ADDR = 011,
+  OUT2_ADDR = 012,
+  OUT3_ADDR = 013,
+  OUT4_ADDR = 014,
+  BANK_ADDR = 015,
+  // No bits in these registers
+  RELINT_ADDR = 016,
+  INHINT_ADDR = 017,
+  // In eraseable memory
+  CYR_ADDR = 020,
+  SR_ADDR = 021,
+  CYL_ADDR = 022,
+  SL_ADDR = 023,
+  ZRUPT_ADDR = 024,
+  BRUPT_ADDR = 025,
+  ARUPT_ADDR = 026,
+  QRUPT_ADDR = 027,
+};
+class regS : public reg
+{
+public:
+  regS() :
+      reg(12, "%04o")
+  {
+  }
+};
+class regBNK : public reg
+{
+public:
+  regBNK() :
+      reg(4, "%02o")
+  {
+  }
+};
+class ADR
+{
+  friend class MON;
+  friend class MEM;
+  friend class CLK;
+  friend class CPM;
+public:
+  static void
+  execWP_WS();
+  static void
+  execRP_RBK();
+  static void
+  execWP_WBK();
+  static bool
+  GTR_17(); // for MBF, CPM
+  static bool
+  GTR_27(); // for PAR
+  static bool
+  EQU_16(); // for CPM
+  static bool
+  EQU_17(); // for CPM
+  static bool
+  EQU_25(); // for SEQ
+  static bool
+  GTR_1777(); // for CPM
+  static unsigned
+  getEffectiveAddress();
+private:
+  static regS register_S; // address register
+  static regBNK register_BNK; // bank register
+  static unsigned
+  bankDecoder();
+  static unsigned conv_WBK[];
+};
+#endif