This repository contains the project 4-bit up/down synchronous counter using esim designed for VSD Mixed Signal Design Hackathon 2022.
The esim folder contains the esim workspace files i.e. model files, makerchip file, ngveri file, plots and simulations all related to esim design and simulation.
The Screenshots Folder contains all the screenshot of simulation and design.
The literature survey and Final Report are also attached herewith.