PDSVM-FPGA

A parallel computing architecture designed for SVM on FPGA

Author : Huaming Shen

Shanghai University

Enviroment: ISE14.7 64bit; FPGA: spartan6lx45-2csg324;

Top File: uart_test.v

external IPcore : 1 PLL, and 1 FIFO; FIFO setting: Native Inteface, Independent Clock Block RAM, Write Width 8, Write Depth 2048, Read Width 8;

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
README.md		README.md
clkdiv.v		clkdiv.v
ddr_verilog.v		ddr_verilog.v
div_cal.v		div_cal.v
exp_top.v		exp_top.v
fifo.xco		fifo.xco
fifo_test.v		fifo_test.v
mul_five.v		mul_five.v
mul_four.v		mul_four.v
mul_one.v		mul_one.v
mul_three.v		mul_three.v
mul_two.v		mul_two.v
multiple_five.v		multiple_five.v
multiple_four.v		multiple_four.v
multiple_three.v		multiple_three.v
multiple_two.v		multiple_two.v
pll.xco		pll.xco
svm_forest.v		svm_forest.v
svm_kernal.v		svm_kernal.v
svm_train.v		svm_train.v
uart_test.v		uart_test.v
uartctrl.v		uartctrl.v
uartrx.v		uartrx.v
uarttx.v		uarttx.v

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