LAB612 Hardware Training problem Sets

1. Every hardware you design must has its datapath drawn and with detailed description about how you do it.
   
2. You have to give a report about your hardware design and verification process all the way from algorithm to synthesis.
   
3. You have to write your own testbenches for your own circuit
   
4. The code you created must be synthesizable
   
5. DATAPATH AND CONTROLPATH HAS TO BE PROVIDED
   
6. You must provide your system diagram
   
7. Must have good Naming Conventions
   

Combinational Logic and Sequential Logic(You have to pass Gate Level Simulation)

1. Parametrizable N-bit Carry look Ahead adder

2. FIR Filter design

3. Random Number Generator(LFSR)

4. 8-value Bitonic Sorter

Basic FSM and Sequential logic design

1. Sequence Detector

2. 3x3 Matrix Computation

3. Traffic Light Controller

4. LIFO

Partitioned design(Datapath and controlpath partitioning)

1. Vending Machine

2. Dice Game

3. IC contest Local Binary Pattern

4. BubbleSort RTL

5. RTL GCD algorithm

6. Circular FIFO

Small IP design (After this Level you can discuss and do these projects together)

1. IC contest Geofence

2. IC contest Image Convolution

3. IC contest Job Assignment

4. ALU supports Floating point calculation

Advanced IP design

1. 32-point FFT Processor

2. IC contest Huffman Coding

3. IC contest String matching Engine

4. RTL Dijkstra Algorithm

5. QR-Cordic

6. Connect6 on FPGA

System Level Design(You have to consider the efficiency and make tradeoff of your HW after this point also add APR)

1. Multicycle MIPS processor with Ideal memory

2. RTL Sudoku

3. RTL 8-Queens problem

4. Most IC lab exercises

5. SHA-3 accelerator

6. IC contest Finals

Advanced system level design

SRAM and DRAM also consideration of Memory Hierachy is needed afterward.

1. Pipelined RISC-V Processor with memory Hierarchy, SRAM and Caches + Memory Controller, Branch predictor and Exception Handling mechanism.

2. AlexNet CNN Accelerator with Memory Hierarchy

3. Hardware Accelerator for Genetic Algorithm

4. IC Lab Mid and Final Projects

SOC and advanced processor or you can start writing your Thesis

Test your design on ZYNQ-FPGA for IP reuse

1. AXI Stream and AMBA arhictecture

2. Super-Scalar OoO RISC-V processor with F-extension

3. AI Accelerator Design with Memory Hierarchy and Processor on FPGA (Eyeriss,ShiDianNao,Gemmini) etc....

4. Multi-Core Processors with Shared memory system and memory controller

5. AES Encryption Engine