/
inmate-zynqmp.dts
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/
inmate-zynqmp.dts
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/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Device tree for Linux inmate test on ZynqMP ZCU102 and Ultra96 boards,
* corresponds to configs/arm64/zynqmp-zcu102-linux-demo.c and
* configs/arm64/ultra96-linux-demo.c.
*
* Copyright (c) Siemens AG, 2016-2019
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
model = "Jailhouse cell on ZynqMP";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
hypervisor {
compatible = "jailhouse,cell";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
gic: interrupt-controller@f6801000 {
compatible = "arm,gic-400";
reg = <0x0 0xf9010000 0x0 0x1000>,
<0x0 0xf902f000 0x0 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
};
uartclk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
uart: serial@ff010000 {
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
reg = <0x0 0xff010000 0x0 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&uartclk>;
clock-names = "uart_clk", "pclk";
};
pci@fc000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
<0 0 0 2 &gic GIC_SPI 109 IRQ_TYPE_EDGE_RISING>,
<0 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
<0 0 0 4 &gic GIC_SPI 111 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xfc000000 0x0 0x100000>;
ranges =
<0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
};
};