SIFIVE FORK NOTES

run a build and upload a release to GitHub whenever a tag is created. You can simply cherry-pick the latest commit on top of a real Verilator release and create a tag from that.

# Note: You should replace 4.028 with whichever version you are trying to use.
git remote add verilator git@github.com:verilator/verilator.git
git fetch verilator
git checkout v4.028
git cherry-pick origin/master -X theirs
# git will likely want you to resolve the fact that the README.adoc and
# .travis.yaml files are not in the repo here.
git add README.adoc
git add .travis.yaml
git cherry-pick --continue
git tag 4.028-0sifive1
git push origin 4.028-0sifive1

For posterity, the old master branch from this SiFive fork with the old instructions for performing a release is available at https://github.com/sifive/verilator/tree/old-master-2018-02-02.

Welcome to Verilator

Welcome to Verilator, the fastest free Verilog HDL simulator. • Accepts synthesizable Verilog or SystemVerilog • Performs lint code-quality checks • Compiles into multithreaded C++, or SystemC • Creates XML to front-end your own tools
	Fast • Outperforms many commercial simulators • Single- and multi-threaded output models
Widely Used • Wide industry and academic deployment • Out-of-the-box support from Arm, and RISC-V vendor IP
	Community Driven & Openly Licensed • Guided by the CHIPS Alliance and Linux Foundation • Open, and free as in both speech and beer • More simulation for your verification budget
Commercial Support Available • Commercial support contracts • Design support contracts • Enhancement contracts

What Verilator Does

Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It "Verilates" the specified synthesizable Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code.

The user writes a little C++/SystemC wrapper file, which instantiates the "Verilated" model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator, or if you are looking for a behavioral Verilog simulator e.g. for a quick class project (we recommend Icarus Verilog for this.) However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and your team is comfortable writing just a touch of C++ code, Verilator is the tool for you.

Performance

Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather than only translate, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC/C++-under-Python module. The results are a compiled Verilog model that executes even on a single-thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators).

Verilator has typically similar or better performance versus the commercial Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is free, so you can spend on computes rather than licenses. Thus Verilator gives you more cycles/dollar than anything else available.

For more information on how Verilator stacks up to some of the other commercial and free Verilog simulators, see the Verilog Simulator Benchmarks. (If you benchmark Verilator, please see the notes in the Verilator manual (PDF), and also if possible post on the forums the results; there may be additional tweaks possible.)

Installation & Documentation

For more information:

• Verilator installation and package directory structure

• Verilator manual (HTML), or Verilator manual (PDF)

• Verilator forum

• Verilator Issues

Support

Verilator is a community project, guided by the CHIPS Alliance under the Linux Foundation.

We appreciate and welcome your contributions in whatever form; please see Contributing to Verilator. Thanks to our Contributors and Sponsors.

Verilator also supports and encourages commercial support models and organizations; please see Verilator Commercial Support.

Related Projects

• GTKwave - Waveform viewer for Verilator traces.

• Icarus Verilog - Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.

Open License

Verilator is Copyright 2003-2020 by Wilson Snyder. (Report bugs to Verilator Issues.)

Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details.