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ariane intial
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@gadfort
gadfort committed Aug 7, 2023
1 parent 9885a92 commit d5879a6
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80 changes: 80 additions & 0 deletions scgallery/designs/ariane/ariane.py
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#!/usr/bin/env python3

import os

from siliconcompiler import Chip
from siliconcompiler.targets import freepdk45_demo
from scgallery.libraries.freepdk45.fakeram45 import fakeram45


def setup(target=freepdk45_demo,
use_cmdline=False):
chip = Chip('ariane')

if use_cmdline:
chip.create_cmdline(chip.design)

mod_root = os.path.dirname(__file__)
src_root = os.path.join(mod_root, 'src')
sdc_root = os.path.join(mod_root, 'constraints')

for src in ('ariane.sv2v.v',):
chip.input(os.path.join(src_root, src))

if not chip.get('option', 'target'):
chip.load_target(target)

mainlib = chip.get('asic', 'logiclib')[0]
sdc = os.path.join(sdc_root, f'{mainlib}.sdc')
if os.path.exists(sdc):
chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'))

if mainlib == 'nangate45':
chip.use(fakeram45)
chip.add('asic', 'macrolib', 'fakeram45_256x16')
chip.input(os.path.join(src_root, 'nangate45', 'macros.v'))

chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'flatten', 'false')
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'rtlmp_enable',
'true')
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'rtlmp_min_instances',
'5000')
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'rtlmp_max_instances',
'30000')
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'rtlmp_min_macros',
'16')
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'rtlmp_max_macros',
'4')

chip.set('constraint', 'outline', [(0, 0),
(1500, 1500)])
chip.set('constraint', 'corearea', [(10, 12),
(1448, 1448)])
for task in ('floorplan', 'place'):
chip.set('tool', 'openroad', 'task', task, 'var',
'ppl_arguments', [
'-exclude left:0-500',
'-exclude left:1000-1500',
'-exclude right:*',
'-exclude top:*',
'-exclude bottom:*'])
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'macro_place_halo',
['10', '10'])
chip.set('tool', 'openroad', 'task', 'floorplan', 'var',
'macro_place_channel',
['20', '20'])

return chip


if __name__ == '__main__':
chip = setup(use_cmdline=True)

chip.run()
chip.summary()
146 changes: 146 additions & 0 deletions scgallery/designs/ariane/src/nangate45/macros.v
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module SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);

input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;

assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable

fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));

endmodule // SyncSpRamBeNx64_00000008_00000100_0_2

// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro
module limping_SyncSpRamBeNx64_00000008_00000100_0_2
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);

input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [63:0] WrData_DI;
input [7:0] Addr_DI;
output [63:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [63:0] RdData_DO;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;

assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable

fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
// fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
// fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
// fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
assign RdData_DO[63:16] = 48'h0;


endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2

module SyncSpRamBeNx64_00000008_00000100_0_2_d45
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);

input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [44:0] WrData_DI;
input [7:0] Addr_DI;
output [44:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;

assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[44:0];

fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]}));

endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45

module SyncSpRamBeNx64_00000008_00000100_0_2_d44
(
Clk_CI,
Rst_RBI,
CSel_SI,
WrEn_SI,
BEn_SI,
WrData_DI,
Addr_DI,
RdData_DO
);

input [7:0] BEn_SI; // byte-enable: ignore or use as needed
input [43:0] WrData_DI;
input [7:0] Addr_DI;
output [43:0] RdData_DO;
input Clk_CI;
input Rst_RBI; // reset: ignore or use as needed
input CSel_SI;
input WrEn_SI;
wire [47:0] RdData_DO_wire;
wire csel_b,wren_b;
wire [15:0] WMaskIn, NotWMaskIn;

assign NotWMaskIn = 16'b0;
assign WMaskIn = ~NotWMaskIn;
assign wren_b = ~WrEn_SI; // active-low global-write-enable
assign csel_b = ~CSel_SI; // active-low chip-select-enable
assign RdData_DO = RdData_DO_wire[43:0];

fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]}));

endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44

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