Merge pull request #1144 from siliconcompiler/noah/klayout-cleanup

Miscellaneous asicflow cleanup

siliconcompiler/tools/klayout/klayout.py

@@ -85,7 +85,7 @@ def setup(chip, mode="batch"):
     else:
         clobber = False
         script = 'klayout_export.py'
-        option = ['-zz', '-r']
+        option = ['-b', '-r']
 
     chip.set('tool', tool, 'exe', klayout_exe)
     chip.set('tool', tool, 'vswitch', ['-zz', '-v'])
@@ -126,25 +126,9 @@ def setup(chip, mode="batch"):
         else:
             chip.error(f'Stackup and targetlib paremeters required for Klayout.')
 
-    logfile = f"{step}.log"
-
     # Log file parsing
-    chip.set('tool', tool, 'regex', step, index, 'warnings', "WARNING", clobber=False)
-    chip.set('tool', tool, 'regex', step, index, 'errors', "ERROR", clobber=False)
-
-################################
-#  Environment setup
-################################
-
-def setup_env(chip):
-    '''
-    Creates environment setup files in the current directory.
-
-    Setup is based on the parameters passed in through the chip object.
-
-    '''
-
-    return 0
+    chip.set('tool', tool, 'regex', step, index, 'warnings', r'(WARNING|warning)', clobber=False)
+    chip.set('tool', tool, 'regex', step, index, 'errors', r'ERROR', clobber=False)
 
 ################################
 #  Custom runtime options

siliconcompiler/tools/klayout/klayout_export.py

@@ -135,17 +135,17 @@ def read_fills(top):
   tech.load(tech_file)
   layoutOptions = tech.load_layout_options
   layoutOptions.lefdef_config.macro_resolution_mode = 1
-  pathed_files = []
+  pathed_files = set()
   for fn in layoutOptions.lefdef_config.lef_files:
     if fn[0:2] == './':
-      pathed_files.append(foundry_lefs + fn[1:])
+      pathed_files.add(foundry_lefs + fn[1:])
     else:
-      pathed_files.append(fn)
+      pathed_files.add(fn)
 
   for lef in macro_lefs:
-    pathed_files.append(lef)
+    pathed_files.add(lef)
 
-  layoutOptions.lefdef_config.lef_files = pathed_files
+  layoutOptions.lefdef_config.lef_files = list(pathed_files)
   layoutOptions.lefdef_config.read_lef_with_def = False
 
   # Load def file

siliconcompiler/tools/openroad/openroad.py

@@ -151,7 +151,7 @@ def setup(chip, mode='batch'):
 
     # basic warning and error grep check on logfile
     chip.set('tool', tool, 'regex', step, index, 'warnings', r'^\[WARNING', clobber=False)
-    chip.set('tool', tool, 'regex', step, index, 'errors', r'ERROR', clobber=False)
+    chip.set('tool', tool, 'regex', step, index, 'errors', r'^\[ERROR', clobber=False)
 
     # reports
     logfile = f"{step}.log"

siliconcompiler/tools/openroad/sc_apr.tcl

@@ -133,7 +133,9 @@ foreach item $sc_scenarios {
 
 # Read Lefs
 foreach lib "$sc_targetlibs $sc_macrolibs" {
-    read_lef [dict get $sc_cfg library $lib model layout lef $sc_stackup]
+    foreach lef [dict get $sc_cfg library $lib model layout lef $sc_stackup] {
+        read_lef $lef
+    }
 }
 
 # Read Verilog

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -77,10 +77,13 @@ yosys opt
 source "$sc_refdir/syn_strategies.tcl"
 
 set script ""
-if {[dict exists $sc_cfg eda $sc_tool variable $sc_step $sc_index strategy]} {
-    set sc_strategy [dict get $sc_cfg eda $sc_tool variable $sc_step $sc_index strategy]
+if {[dict exists $sc_cfg tool $sc_tool var $sc_step $sc_index strategy]} {
+    set sc_strategy [dict get $sc_cfg tool $sc_tool var $sc_step $sc_index strategy]
     if { [dict exists $syn_strategies $sc_strategy] } {
         set script [dict get $syn_strategies $sc_strategy]
+    } elseif { [string match "+*" $sc_strategy] } {
+        # ABC script passthrough
+        set script $sc_stratety
     } else {
         puts "Warning: no such synthesis strategy $sc_strategy"
     }

siliconcompiler/tools/yosys/yosys.py

@@ -1,6 +1,5 @@
 import os
 import re
-import os
 import shutil
 import importlib
 from jinja2 import Template