Merge pull request #1157 from siliconcompiler/0.9.6

Release 0.9.6
siliconcompiler · Oct 4, 2022 · 77f2f47 · 77f2f47
2 parents 8bcd174 + b777cee
commit 77f2f47
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diff --git a/Changes b/Changes
@@ -8,6 +8,23 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.9.6 (2022-10-03)
+=========================================
+
+**Major:**
+
+* Fixed bug that causes tool setup information to be lost when running a flow in multiple chunks using a steplist.
+
+**Minor:**
+
+* Fixed old schema references in Yosys synthesis strategy scripts.
+* Updated error message for missing file requirements.
+* Updated OpenROAD scripts to handle multiple LEF files.
+* Updated KLayout driver to use batch mode flag and capture more warnings.
+* Updated Verilator driver to implement ['option', 'trace], ['option', 'warningoff'], and provide passthroughs for CFLAGS and LDFLAGS.
+* Removed support for 'extraopts' passthrough in Verilator driver.
+* Updated version of Surelog bundled with wheels distribution.
+
 SiliconCompiler 0.9.5 (2022-09-12)
 =========================================
 

diff --git a/siliconcompiler/_metadata.py b/siliconcompiler/_metadata.py
@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.9.5'
+version = '0.9.6'
 
 # This is the list of significant contributors to SiliconCompiler in
 # chronological order.