Merge pull request #2240 from siliconcompiler/update-yosys

Update yosys

.github/workflows/daily_ci.yml

@@ -87,15 +87,12 @@ jobs:
     steps:
       - name: Checkout SiliconCompiler
         uses: actions/checkout@v4
-        with:
-          submodules: true
 
       - name: Checkout ZeroSOC
         uses: actions/checkout@v4
         with:
           repository: siliconcompiler/zerosoc
           path: zerosoc
-          submodules: true
 
       - name: Run flat
         if: matrix.config == 'flat'

setup/_tools.json

@@ -85,7 +85,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "yosys-0.38",
+    "git-commit": "yosys-0.39",
     "version-prefix": "yosys-",
     "auto-update": true
   },

siliconcompiler/tools/yosys/prepareLib.py

@@ -4,10 +4,9 @@
 import re
 import gzip
 import argparse  # argument parsing
-import fnmatch
 
 
-def processLibertyFile(input_file, dont_use=None, logger=None):
+def processLibertyFile(input_file, logger=None):
     # Read input file
     if logger:
         logger.info(f"Opening file for replace: {input_file}")
@@ -18,28 +17,6 @@ def processLibertyFile(input_file, dont_use=None, logger=None):
     content = f.read().encode("ascii", "ignore").decode("ascii")
     f.close()
 
-    if dont_use:
-        # Pattern to match a cell header
-        patternList = [re.compile(fnmatch.translate(du)) for du in dont_use]
-
-        content_dont_use = ""
-        re_cell_line = re.compile(r"^\s*cell\s*\(\s*[\"]?(\w+)[\"]?\)\s*\{")
-        count = 0
-        for line in content.splitlines():
-            content_dont_use += line + "\n"
-            cell_match = re_cell_line.match(line)
-            if cell_match:
-                for du in patternList:
-                    if du.match(cell_match.group(1)):
-                        if logger:
-                            logger.info(f'  Marking {cell_match.group(1)} as dont_use')
-                        content_dont_use += "    dont_use : true;\n"
-                        count += 1
-                        break
-        content = content_dont_use
-        if logger:
-            logger.info(f"Marked {count} cells as dont_use")
-
     # Yosys-abc throws an error if original_pin is found within the liberty file.
     # removing
     pattern = r"(.*original_pin.*)"

siliconcompiler/tools/yosys/syn_asic.py

@@ -186,23 +186,11 @@ def prepare_synthesis_libraries(chip):
     # mark dff libery file with dont use
     dff_liberty_file = chip.find_files('tool', tool, 'task', task, 'file', 'dff_liberty',
                                        step=step, index=index)[0]
-    dff_dont_use = []
-    for lib in chip.get('asic', 'logiclib', step=step, index=index):
-        dontuse = chip.get('library', lib, 'asic', 'cells', 'dontuse', step=step, index=index)
-        if dff_liberty_file in chip.find_files(*_get_synthesis_library_key(chip, lib, corners),
-                                               step=step, index=index):
-            # if we have the exact library, use those dontuses,
-            # otherwise continue to build full list
-            dff_dont_use = dontuse
-            break
-
-        dff_dont_use.extend(dontuse)
 
     with open(chip.get('tool', tool, 'task', task, 'file', 'dff_liberty_file',
                        step=step, index=index)[0], 'w') as f:
         f.write(prepareLib.processLibertyFile(
             dff_liberty_file,
-            dont_use=dff_dont_use,
             logger=None if chip.get('option', 'quiet', step=step, index=index) else chip.logger
         ))
 

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -236,7 +236,14 @@ if {[dict get $sc_cfg tool $sc_tool task $sc_task var autoname] == "true"} {
     yosys autoname
 }
 
-yosys dfflibmap -liberty $sc_dff_library
+set dfflibmap_dont_use []
+foreach lib "$sc_logiclibs $sc_macrolibs" {
+    foreach cell [dict get $sc_cfg library $lib asic cells dontuse] {
+        lappend dfflibmap_dont_use -dont_use $cell
+    }
+}
+
+yosys dfflibmap {*}$dfflibmap_dont_use -liberty $sc_dff_library
 
 # perform final techmap and opt in case previous techmaps introduced constructs that need
 # techmapping

siliconcompiler/tools/yosys/yosys.py

@@ -41,7 +41,7 @@ def setup(chip):
     # Standard Setup
     chip.set('tool', tool, 'exe', 'yosys')
     chip.set('tool', tool, 'vswitch', '--version')
-    chip.set('tool', tool, 'version', '>=0.33+21', clobber=False)
+    chip.set('tool', tool, 'version', '>=0.38+92', clobber=False)
     chip.set('tool', tool, 'format', 'tcl', clobber=False)
 
     # Task Setup