This is a 5-stage pipeline RISC-V simulator written in Rust.
- All RV32I base instruction set.
- Some RV32M instructions, such as
mul
,mulh
,mulhu
.
- RV32I base instruction set
- Assembler
- 5-stage pipeline
- data hazard and control hazard
- Visualization
- more instructions
To build the simulator, you will need to have Rust installed. You can get Rust from rustup.
Once you have Rust installed, you can build the simulator by running
cargo build
in the root of the repository.
Usage: rvsim [OPTIONS] <PATH>
Arguments:
<PATH> Input assembly file
Options:
-v, --verbose Print pipeline info for each cycle
-a, --analysis Print analysis info
-s, --step Step running
-h, --help Print help
-V, --version Print version
It uses data forwarding and stalling to solve data hazard and control hazard. And it will stall one cycle when branch instruction occurs and load instruction hazard.
ebreak
will stop the program and need you to press enter to continueecall
only supportsexit
now. And it will check whethera0
is17
, and takea1
as exit code.
- It doesn't support pseudo instruction now.
- It doesn't support multi file linking now. And
.globl
will take its first label as entry point. - It supports
.data
and.code
..data
can only put.string
,.word
,.half
and.byte
now. And.code
can only put instructions now. - Its output endian is little endian.
You can see some examples in tests
directory.
tests/1.s
is a simple example without any hazards.tests/2.s
is a simple example with RAW data hazard.tests/3.s
is a simple example with branch jump.tests/matrix.s
is a matrix multiplication example.