Fixing bug in write out.

simpeg · Apr 8, 2016 · 90b0301 · 90b0301
1 parent 083742c
commit 90b0301
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/SimPEG/Directives.py b/SimPEG/Directives.py
@@ -222,7 +222,7 @@ def endIter(self):
             mref = 0
         mx = self.reg.Wx * ( self.reg.mapping * (self.invProb.curModel - mref) )
         phi_mx = 0.5 * mx.dot(mx)
-        if self.prob.mesh.dim < 2:
+        if self.prob.mesh.dim >= 2:
             my = self.reg.Wy * ( self.reg.mapping * (self.invProb.curModel - mref) )
             phi_my = 0.5 * my.dot(my)
         else: