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Fastino

Specs

• 32 channels, 2 M/s (1/512 ns) simultaneous, 16 bit: 1 Gb/s aggregate
  • AD5542ABCPZ 1us settling time, >2.7 V
• AFE/DAC: from Stabilizer, maybe modified, similar bandwidth, range
• Interface: single EEM (more EEM if there are pins and space)
  • CLK bit clock at e.g. 125 MHz
  • CS/frame/LDAC
  • MISO for clock alignment/readback/configuration/version/identification (slow, at e.g. CLK/16, to not worry about round trip delays)
  • MOSI0 for configuration/command/identification/masking/clear
  • MOSI1 DAC data DDR 250 Mb/s
  • MOSI2 DAC data DDR 250 Mb/s
  • MOSI3 DAC data DDR 250 Mb/s
  • MOSI4 DAC data DDR 250 Mb/s
• out-of-band channel to control:
  • Data/clock/LDAC masking on channels for intervals to suppress digital feedthrough
  • LEDs
  • no contention between configuration and data
  • Update rate on DAC masking: ~1 µs

Components

• HW specification/review/codesign/input
• Phy layer of framed data at 1 Gb/s over multilane LVDS with slower return channel (1 EEM), serialization/deserialzation/framing
  • this sounds very much like channel link/camera link, TI serdes chips.
• DAC interface: PLL for SPI bitclock, sample clocking, CLR, LDAC
• Out-of-band configuration layer: configuration, LEDs, clocking, channel masking
• RTIO channel design
  • baseline: 32x16 bit=512 bit DAC data events on existing kernel/DMA/DRTIO infrastructure
  • later: optimize DMA/Fastino-DMA/DRTIO/DDMA to achieve 2 M/s 512 b events
• ARTIQ coredevice API
• docs, examples, tests
• CI
• Option: Interpolator to 2 MS/s @ 32 channels

API

• identify
• set LEDs
• TBD: tune clock skew?
• set masked channels
• submit DAC data (all channels)
• later option: interpolation ratio
• later option: 2D arrays of a configurable subset of channels at given sample rate
• later option: per-channel sine generation (e.g. for tickling)
• later option: per-channel offsets in gateware (e.g. compensate stray fields without re-uploading shuttling waveforms) or composing waveforms
• later option: per-channel clipping/limiting in gateware
• later option: dynamic/configurable sample clock alignment to below the DAC granularity, i.e. variable sample phase

Roadmap

• Prototype serializer/deserializer on Kasli+Banker/Humpback
• Measure RTIO/DMA/DRTIO throughput at 512b events
• Hardware
• DAC interface
• RTIO components
• Masking/configuration/version/identification channel
• coredevice API