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Joe Britton edited this page Feb 18, 2022 · 13 revisions

Phaser

Quad channel 1.25 GS/s RF generator card with dual IQ upconverter and dual 5 MS/s ADC and FPGA in EEM form factor

Design files (schematics, PCB layouts, BOMs) can be found at Phaser/releases.

  • layout variant Phaser_Baseband has no dual IQ mixer
  • layout variant Phaser_Upconverter is populated with the dual IQ mixer.

Overview

  • 4 channel 625 MS/s from FPGA
  • 4 channels of 1.25 GS/s 16-bit parallel DAC (DAC34H84)
  • dual IQ mixer + 0.3 GHz to 4.8 GHz VCO + PLL (TRF372017)
  • 31.5 dB range digital step attenuator (like Urukul)
  • 2 channels of 5 MS/s ADC, using a 2-channel version of Sampler/BaseMod
  • Artix xc7a100t/15t FPGA
  • Internal MMCX clock from Kasli/Clocker and external SMA
  • 2 EEM connectors

Gateware

  • 5 tone 25 MS/s IQ DDS per channel in coredevice gateware
  • IQ sample stream over 1.5 Gb/s EEM link
  • 20x interpolation from 25 MS/s to 500 MS/s
  • digital upconversion in gateware on Phaser
  • deterministic latency
  • interfaces to all spi buses and peripherals

https://github.com/quartiq/phaser

Norman Krackow's STFT master thesis and the two talks also contain a useful introduction to Phaser.

Photo

Operational Notes

  • v1.0 and v1.1 require forced air cooling (link).
  • For the upconverter variant, IQ modulation that involves a DC component is not supported (link).