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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <DxArchiverProject version="1"> | ||
| <DxProject Path="./ARTIQ.prj"/> | ||
| <TargetDirectory Path="D:\Dropbox\DESIGNS\MTCA projects\SINARA\ARTIQ_EE\ProjectBackup\xDx_archives_GK"/> | ||
| <Compression Type="Zip"/> | ||
| <PDF Type="0"/> | ||
| <SetSTATIC Type="0"/> | ||
| <AdditionalFiles> | ||
| </AdditionalFiles> | ||
| </DxArchiverProject> |
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| <?xml version="1.0"?> | ||
| <DxDesigner_Configuration_file version="1.2" name="DxDesigner.xml"> | ||
| <DxDesigner> | ||
| <SETTINGS> | ||
| <key name="DOTSIZE" value= "50800"/> | ||
| <key name="BOXSIZE" value= "101600"/> | ||
| <key name="BUBBLESIZE" value= "50800"/> | ||
| <key name="BUS_DOTSIZE" value= "76200"/> | ||
| <key name="BUSWIDTH" value= "50800"/> | ||
| <key name="DEFAULT_ZOOM" value= "0"/> | ||
| <key name="EXPEDITION_ZOOM" value= "1"/> | ||
| <key name="DOTSIZE_HR" value= "2540"/> | ||
| </SETTINGS> | ||
| <OBJECTS> | ||
| <object name="NET"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| <key name="FILL_STYLE" value= "1"/> | ||
| </object> | ||
| <object name="ATTRIBUTE"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| <key name="FILL_STYLE" value= "5"/> | ||
| </object> | ||
| <object name="LABEL"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| <key name="FILL_STYLE" value= "5"/> | ||
| </object> | ||
| <object name="PIN"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| <key name="FILL_STYLE" value= "1"/> | ||
| <key name="LINE_STYLE" value= "0"/> | ||
| </object> | ||
| <object name="BOX"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </object> | ||
| <object name="LINE"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </object> | ||
| <object name="CIRCLE"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </object> | ||
| <object name="ARC"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </object> | ||
| <object name="TEXT"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| <key name="FILL_STYLE" value= "5"/> | ||
| </object> | ||
| </OBJECTS> | ||
| <LAYERS> | ||
| <layer name="SELECTION_LAYER"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </layer> | ||
| <layer name="BORDER_LAYER"> | ||
| <key name="COLOR" value= "0x000000"/> | ||
| </layer> | ||
| <layer name="BACKGROUND_LAYER"> | ||
| <key name="COLOR" value= "0xffffff"/> | ||
| </layer> | ||
| </LAYERS> | ||
| </DxDesigner> | ||
| </DxDesigner_Configuration_file> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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| SECTION iCDB | ||
| LIST Designs | ||
| VALUE "Sayma_RTM" | ||
| ENDLIST | ||
| KEY DedicatedServerName "" | ||
| KEY iCDBDir ".\database" | ||
| ENDSECTION | ||
| SECTION TestMod_SEAx_Base | ||
| KEY ConfigType "PCB" | ||
| KEY RootBlock "TestMod_SEAx_Base" | ||
| KEY SearchPathScheme "(Default)" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SchematicConflict "FE" | ||
| ENDSECTION | ||
| SECTION Metlino_MCH | ||
| KEY AllowAlpha "0" | ||
| KEY CADBackAnno "0" | ||
| KEY ConfigType "PCB" | ||
| KEY DisableBackAnnoChanges "0" | ||
| KEY DisableECOChanges "0" | ||
| KEY FanoutSinglePinNets "0" | ||
| KEY FwdAnnoCleanBuildFlag "0" | ||
| KEY FwdAnnoExtractFlag "1" | ||
| KEY FwdAnnoRebuildFlag "0" | ||
| KEY FwdAnnoRemoveHangers "1" | ||
| KEY FwdAnnoRemoveTraces "1" | ||
| KEY FwdAnnoReplaceFlag "0" | ||
| KEY FwdAnnoSchematicRefDesChanges "1" | ||
| KEY LayoutTemplate "12 Layer Template" | ||
| KEY PCBDesignPath "PCB_Metlino\Metlino.pcb" | ||
| KEY PCBForwardAnno "1" | ||
| KEY RootBlock "Metlino_MCH" | ||
| KEY SchematicConflict "FE" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SearchPathScheme "(Default)" | ||
| KEY UnusedPartsFlag "0" | ||
| KEY UpdateJobPrefsDB "CAD" | ||
| ENDSECTION | ||
| SECTION AMC_FMC_Carrier | ||
| KEY AllowAlpha "1" | ||
| KEY CADBackAnno "1" | ||
| KEY ConfigType "PCB" | ||
| KEY FwdAnnoCleanBuildFlag "0" | ||
| KEY FwdAnnoExtractFlag "0" | ||
| KEY FwdAnnoRebuildFlag "0" | ||
| KEY FwdAnnoReplaceFlag "1" | ||
| KEY LayoutTemplate "12 Layer Template" | ||
| KEY PCBDesignPath "PCB\AMC_FMC_ZQ.pcb" | ||
| KEY PCBForwardAnno "1" | ||
| KEY RootBlock "AMC_FMC_ZQ_Carrier" | ||
| KEY SchematicConflict "FE" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SearchPathScheme "(Default)" | ||
| KEY UpdateJobPrefsDB "CAD" | ||
| ENDSECTION | ||
| SECTION CESDiagnostics_DxD | ||
| KEY DESIGN_CHECK_LAST_UPDATE "2017-02-27 00:18:49" | ||
| KEY DESIGN_CHECK_NUM_ERRORS "0" | ||
| ENDSECTION | ||
| SECTION CESDiagnostics_Sayma_AMC_Layout_Temp | ||
| KEY DESIGN_CHECK_LAST_UPDATE "2018-08-10 21:41:56" | ||
| KEY DESIGN_CHECK_NUM_ERRORS "2" | ||
| ENDSECTION | ||
| SECTION DesignInfo | ||
| LIST HdlSearchPaths | ||
| ENDLIST | ||
| KEY BorderSymbols "D:\Dropbox\DESIGNS\MTCA_projects\SINARA\ARTIQ_EE\borders.ini" | ||
| KEY Bus_Contents "D:\Dropbox\DESIGNS\MTCA_projects\SINARA\ARTIQ_EE\busconts.ini" | ||
| KEY CentralLibrary "D:\Dropbox\DESIGNS\COMMON_LIBS\Xpedition_lib\EXP_CERN_PCB_LIB\EXP_CERN_PCB_LIB.lmc" | ||
| KEY CrossProbing "Off" | ||
| KEY DBCFile "D:\Dropbox\DESIGNS\COMMON_LIBS\Xpedition_lib\EXP_CERN_PCB_LIB\EXP_CERN_PCB_LIB.dbc" | ||
| KEY DxD_Version "XENTPVX.2.2" | ||
| KEY FrontEndSnapshot "DxD" | ||
| KEY HdlUtilsConfigFile "hdlutils.ini" | ||
| KEY NumberingType "INDEPTH" | ||
| KEY OrderFileName ".\" | ||
| KEY PartListerCfg "PartsListerDefaults" | ||
| KEY PinComponents "D:\Dropbox\DESIGNS\MTCA_projects\SINARA\ARTIQ_EE\speccomp.ini" | ||
| KEY SheetsEditMode "1" | ||
| ENDSECTION | ||
| SECTION FlowSettings | ||
| KEY FlowType "DX" | ||
| ENDSECTION | ||
| SECTION ICXProInfo | ||
| KEY HighSpeedPathsVersion "1" | ||
| KEY IBISModelMgrDir "./HighSpeed/ICXPro/Model_Manager" | ||
| KEY ICXProDir "./HighSpeed/ICXPro" | ||
| KEY ICXProDir_old "ICXPro" | ||
| KEY LocalModelsDir "./HighSpeed/ICXPro/Local_Models" | ||
| KEY PostLayoutExplorerDir "./HighSpeed/ICXPro/PostLayoutExplorer" | ||
| KEY PostLayoutLineSim "./HighSpeed/HyperLynx/PostLayoutLineSim" | ||
| KEY SimTemplatesDir "./HighSpeed/ICXPro/Simulation_Templates" | ||
| KEY VerifyDir "./HighSpeed/ICXPro/Verify" | ||
| KEY VerifyLogFilesDir "./HighSpeed/ICXPro/Verify/LogFiles" | ||
| KEY VerifyResultsDir "./HighSpeed/ICXPro/Verify/DataBases" | ||
| KEY VerifySandBoxDir "./HighSpeed/ICXPro/Verify" | ||
| KEY VerifyWaveformsDir "./HighSpeed/ICXPro/Verify/Waveforms" | ||
| ENDSECTION | ||
| SECTION IODesignerData | ||
| KEY DesignFlow "Schematic Export" | ||
| ENDSECTION | ||
| SECTION PCBFwdAnnoOptions | ||
| KEY RootSchematicFile "Sayma_RTM" | ||
| ENDSECTION | ||
| SECTION ProjectBackup | ||
| KEY ConfigFile ".\ProjectBackup\ProjectBackup.cfg" | ||
| ENDSECTION | ||
| SECTION Sayma_RTM | ||
| KEY AllowAlpha "0" | ||
| KEY CADBackAnno "0" | ||
| KEY ConfigType "PCB" | ||
| KEY DisableBackAnnoChanges "0" | ||
| KEY DisableECOChanges "0" | ||
| KEY FanoutSinglePinNets "0" | ||
| KEY FwdAnnoCleanBuildFlag "1" | ||
| KEY FwdAnnoExtractFlag "0" | ||
| KEY FwdAnnoRebuildFlag "0" | ||
| KEY FwdAnnoRemoveHangers "0" | ||
| KEY FwdAnnoRemoveTraces "0" | ||
| KEY FwdAnnoReplaceFlag "0" | ||
| KEY FwdAnnoSchematicRefDesChanges "1" | ||
| KEY LayoutTemplate "12 Layer Template" | ||
| KEY PCBDesignPath "PCB_Sayma_RTM\Sayma_RTM.pcb" | ||
| KEY PCBForwardAnno "1" | ||
| KEY RootBlock "Sayma_RTM" | ||
| KEY SchematicConflict "FE" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SearchPathScheme "(Default)" | ||
| KEY UnusedPartsFlag "1" | ||
| KEY UpdateJobPrefsDB "CAD" | ||
| KEY VMMode "Physical" | ||
| ENDSECTION | ||
| SECTION Template_Design | ||
| KEY CADBackAnno "0" | ||
| KEY ConfigType "PCB" | ||
| KEY SchematicConflict "FE" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SearchPathScheme "(Default)" | ||
| ENDSECTION | ||
| SECTION VBPCBDesignData | ||
| KEY VBPCBDesignPath "PCB\PCB\WR-MCH.pcb" | ||
| ENDSECTION | ||
| SECTION VBPCBIndicators | ||
| KEY AllowAlpha "0" | ||
| KEY CADBackAnno "0" | ||
| KEY DisableBackAnnoChanges "0" | ||
| KEY FanoutSinglePinNets "0" | ||
| KEY FwdAnnoCleanBuildFlag "0" | ||
| KEY FwdAnnoExtractFlag "1" | ||
| KEY FwdAnnoRebuildFlag "0" | ||
| KEY FwdAnnoRemoveHangers "1" | ||
| KEY FwdAnnoRemoveTraces "1" | ||
| KEY FwdAnnoReplaceFlag "0" | ||
| KEY FwdAnnoSchematicRefDesChanges "1" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY UnusedPartsFlag "0" | ||
| KEY VBPCBForwardAnno "0" | ||
| ENDSECTION | ||
| SECTION WR-MCH | ||
| LIST IODesignerData | ||
| ENDLIST | ||
| KEY AllowAlpha "0" | ||
| KEY CADBackAnno "0" | ||
| KEY ConfigType "PCB" | ||
| KEY DisableBackAnnoChanges "0" | ||
| KEY FanoutSinglePinNets "0" | ||
| KEY FwdAnnoCleanBuildFlag "0" | ||
| KEY FwdAnnoExtractFlag "0" | ||
| KEY FwdAnnoRebuildFlag "1" | ||
| KEY FwdAnnoRemoveHangers "1" | ||
| KEY FwdAnnoRemoveTraces "1" | ||
| KEY FwdAnnoReplaceFlag "0" | ||
| KEY FwdAnnoSchematicRefDesChanges "1" | ||
| KEY LayoutTemplate "8 Layer Template" | ||
| KEY PCBDesignPath "PCB_Tongue2\WR-MCH.pcb" | ||
| KEY PCBForwardAnno "0" | ||
| KEY RootBlock "WR-MCH-TOP" | ||
| KEY SchematicConflict "FE" | ||
| KEY SchematicDesignBackAnno "0" | ||
| KEY SchematicDesignStatus "0" | ||
| KEY SearchPathScheme "(Default)" | ||
| KEY UnusedPartsFlag "0" | ||
| KEY UpdateJobPrefsDB "CAD" | ||
| ENDSECTION |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,62 @@ | ||
| <?xml version="1.0"?> | ||
| <VDRC> | ||
| <FlowType Name="Expedition"/> | ||
| <GUI Name="Default"> | ||
| <Settings/> | ||
| <Rules> | ||
| <Group Name="Interconnectivity"/> | ||
| <Group Name="Migration"/> | ||
| <Group Name="Connectivity"> | ||
| <Check Name="UnconnectedPins" State="Enabled"/> | ||
| <Check Name="UnrippedNet" State="Enabled"/> | ||
| <Check Name="NetOverlap" State="Enabled"/> | ||
| <Check Name="UndrivenCompPins" State="Enabled"/> | ||
| <Check Name="OutputDirectlyPG" State="Enabled"/> | ||
| <Check Name="InputSameComp" State="Enabled"/> | ||
| <Check Name="DipolePinsShorted" State="Enabled"/> | ||
| <Check Name="ConnectivityChecks" State="Enabled"/> | ||
| <Check Name="OnePinNet" State="Enabled"/> | ||
| <Check Name="WidePin" State="Enabled"/> | ||
| <Check Name="NetClass" State="Enabled"/> | ||
| <Check Name="WidePinWidth" State="Enabled"/> | ||
| <Check Name="DanglingPins" State="Enabled"/> | ||
| <Check Name="NetAlias" State="Enabled"/> | ||
| <Check Name="NamedTerms" State="Enabled"/> | ||
| </Group> | ||
| <Group Name="Electrical"/> | ||
| <Group Name="Hierarchy"> | ||
| <Check Name="PinMatch" State="Enabled"/> | ||
| <Check Name="NoNetSpn" State="Enabled"/> | ||
| <Check Name="CompositeMissingSchematic" State="Enabled"/> | ||
| <Check Name="DifferentHierarchicalNetConnected" State="Enabled"/> | ||
| </Group> | ||
| <Group Name="Integrity"> | ||
| <Check Name="ComponentOverlap" State="Enabled"/> | ||
| <Check Name="PinSymWrongType" State="Enabled"/> | ||
| </Group> | ||
| <Group Name="Power&Ground"> | ||
| <Check Name="DriveGlobal" State="Enabled"/> | ||
| <Check Name="InvalidGlobal" State="Enabled"> | ||
| <Option Name="legal_globals" Value=""P3V3" "P1V8" "P2V5" "P0V95" "P0V85" "P1V2" "P1V5_BAT" "P1V2XR" "P1V8XR" "P1V8_MGT" "P1V8_ULPI" "P1V8_USB" "P1V8_VCCADC" "P1V8_VCCPSADC" "P2V5LDO" "P2V5_CLK" "P2V5_VREF" "P3V3_AVDD" "P3V3MP" "P3V3MP_RTM" "P3V3MP_SW" "P3V3_XR" "P3V3_CDR" "P3V3_CLEAN" "P3V3_Si5341" "P5V0" "P12V0" "P12V0_RTM" "P1V8_PSDDRPLL" "P1V8_MGTVCCAUX" "P1V8_MGTRAVTT" "P1V2_PSPLL" "P1V2_MGTAVTT" "P0V85_VCU" "P0V85_MGTRAVCC" "P0V9_MGTAVCC" "P1V8_PSDDRPLL" "P1V8_MGTVCCAUX" "P1V8_MGTRAVTT" "P0V85_MGTRAVCC" "P1V2_PSPLL" "VTT16" "VTT32" "VTT72" "VUSB" "AVDD" "P1V2_MGTAVTT" "P0V85_VCU" "P0V9_MGTAVCC" "MUX1_VDD_CLK00" "MGTVCCAUX" "MUX1_VDD" "GND" "P1V8_Si5341" "P3V3_Si5341" "MUX1_VDD_DIG" "MUX1_VDD" "MUX1_VDD_CLK01" "MUX1_VDD_CLK02" "MUX1_VDD_CLK03" "MUX1_VDD_CLK04" "MUX1_VDD_CLK05" "MUX1_VDD_CLK06" "MUX1_VDD_CLK07" "MUX1_VDD_CLK08" "MUX1_VDD_CLK09" "MUX1_VDD_CLK10" "MUX1_VDD_CLK11" "MUX1_VDD_CLK12" "MUX1_VDD_CLK13" "MUX1_VDD_CLK14" "MUX1_VDD_CLK15" "VTT16" "VTT64" "VTT72" "P3V3_USB" "PAYLOAD_PWR" "P3V3_SW" "P3V3AVDD" "P0V85_MGT" "P1V8SOC""/> | ||
| </Check> | ||
| <Check Name="InvalidLocal" State="Enabled"/> | ||
| <Check Name="GlobalSignals" State="Enabled"/> | ||
| <Check Name="SupNegConnected" State="Enabled"/> | ||
| <Check Name="SupNotConnected" State="Enabled"/> | ||
| <Check Name="SupWrongConnected" State="Enabled"/> | ||
| <Check Name="BlockPinConnectedGlobal" State="Enabled"/> | ||
| <Check Name="NumberConnDevice" State="Enabled"/> | ||
| <Check Name="PowerGroundPinConnection" State="Enabled"/> | ||
| </Group> | ||
| <Group Name="Device Specific"> | ||
| <Check Name="BusTranscPin" State="Enabled"/> | ||
| <Check Name="MultiPinCapacitor" State="Enabled"/> | ||
| </Group> | ||
| <Group Name="HDL Checks"/> | ||
| <Group Name="Links"> | ||
| <Check Name="SheetLinksPointsNowhere" State="Enabled"/> | ||
| <Check Name="UnnamedSheetLinks" State="Enabled"/> | ||
| </Group> | ||
| </Rules> | ||
| </GUI> | ||
| </VDRC> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,15 @@ | ||
| [SYMBOLS] | ||
| A2SHEETL1=Borders:a2sheet.1 | ||
| A2SHEETP1=Borders:a2sheet.2 | ||
| A3SHEETL=Borders:a3sheet_WUT.1 | ||
| A3SHEETL1=Borders:a3sheet_WUT.1 | ||
| A3SHEETP1=Borders:a3sheet.2 | ||
| A4SHEETL1=Borders:a4sheet.1 | ||
| A4SHEETP1=Borders:a4sheet.2 | ||
| [ATTRIBUTES] | ||
| Drawing Author=G.Kasprowicz | ||
| Drawing Number= | ||
| Drawing Project=AMC FMC Carrier Board | ||
| Drawing Revision=1.0 | ||
| [ANNOTATIONS] | ||
| [DEFAULTS] |
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