Sayma AMC - Version 1 errata

[gkasprow]

Mechanical:

• use 2mm higher J14 connector. Wurth 621 010 210 21
• add cutout in the panel under SFP cage to make module removal easier
• make 3.5mm switch hole in front panel
• panel switch hole = 3.5mm
• sfp cutout 0.5mm bottom
• make USB connector hole touch panel edge
• move L23 away from ufl connector
• Move power supply status LEDS from bottom side of board to top edge of board (like on Sayma_RTM) so that they're visible from top of crate.

BOM:

• mark R257 DNP
• add SMA insulating washer to the panel
• wrong type of guiding socket - should be "1" instead of '8'
• IC24=DNP
• R183=DNP
• remove C282
• AMC: make C221 0R to enable internal reference
• install R507 by default
• Include FMC standoffs and screws in BOM.

I2C:

• connect some I2C pullups to P3V3 instead of P3V3MP

JTAG:

• add 0R resistors on SWD/JTAG or FET that disconnects SCANSTA during CPU flashing
• add JTAG MPSEL status/control to MMC pin E8
• fix issue with JTAG switchover. After changing MMPSELB1/B0 SCANSTA needs reset to apply settings
• to enable FLASH programming operation, disconnect it from RTM FPGA. Add termination.
• fix second FLASH CSn connection - use pin G26 for CSn instead of K21

USB:

• T23 source = GND
• Insertion/removal of USB cable resets MMC and power supply. Feature: add RC delay circuit or voltage supervisor. Quick fix: jumper on reset signal on T21
• 100k resistor on T23 gate

Ethernet:

• Make sure that TX CLK goes first before Ethernet PHY reset. Feature: trigger it by CONFIG DONE or leave as it is.
• MAX PHY need to have clock delivered to both MII TX CLK and GTXCLK
• make sure that PHY TRSTn is low
• make sure that PHY LOS is low
• Apply Etheret fix #327

Power:

• feature: add slow start for P12V FMC and RTM 1k5 + 1uF
• add slow start MOSFET in parallel to the current limiting resistor.
• add 3v3mp LED
• add 12V ext TVS
• LD11 current too low, R242 = 10k
• increase the VCCINT to 0.975V
• 0.9V generation - R243+R244=5k1
• swap PSIO2 and GPIO0 - resistors R208, R205

Schematics:

• MAX6642 address is 0x48, not 0x24 - change schematic annotation
• fix schematic symbol of SATA connector - pins numbering
• RTM IC40 address is 0x4B - change comment on schematics
• Fix illegible blocks in schematic (cf #231)
• Zero-index all channels (SMAs, FMCs, SFPs, etc)
• Rename USR_UART_P/N - UART is not a differential signal

Clocks:

• OSC3 = 510BBA200 instead of 510ABA200 or add 2x200R to GND
• wrong connection of SD pins of LTC6957. They must be tied low instead of high.
• re-route Si5324 clocks so CLK1 and CLK2 have same skew - are connected to clock buffer.

Other:

• Assign clock capable pins on FMCs
• wrong pin numbering on J13 silkscreen
• swap T20, T21 drains or gates
• 10k pullup on SFP pin 9
• The SMA_IO1_DIR MOSFET incorrectly controls the SMA_IO2 channel, and vice versa.

RTM:

• replace MAX6642ATT90+T with MAX6642ATT98+T on RTM - change I2C address from 0x48 to 0x4C (already in RTM errata)

[hartytp]

Also, use clock capable pins on FMC if possible (#217).

[gkasprow]

FMC has clock capable pins (LA00CC, LA01CC,LA17CC,LA18CC, M2C) already connected in right way.

[jordens]

Are those also the respective EEM CC pins when using an FMC-VHDCI adapter to drive Kasli-style extensions? That would be an unlikely coincidence.

[gkasprow]

@jordens No, they are not.
VHDCI pinout follows FMC one for easier PCB routing.

[gkasprow]

@hartytp @jordens
There are 2 ways to fix this issue - modify FMC-VHDCI adapter or VHDCI breakout board.
In second case, Metlino would have to be adapted, but it is not a big deal.
SInce we are going to make corrections to VHDCI breakout, this is the right moment to fix this issue.

[hartytp]

I'd modify the VHDCI carrier, and keep the FMC-VHDCI adapter as is.

[jordens]

I would also alter the VHDCI breakout. The good thing is that even with the current boards the odd EEMs are wired sufficiently, see sinara-hw/sinara#217 (comment)

[hartytp]

@gkasprow If you've ordered the Sayma AMCs, does that mean you've already fixed all these bugs? If so, can we close this issue now?

[gkasprow]

@hartytp I mean that I assemble remaining 8 boards which are identical with 2 already produced. They still have some bugs that I have to fix once they are produced. The list of bugs is probably not complete - some of them will emerge during tests with JESD204b. Later on I will implement all fixes in new release of Sayma AMC board and then this issues will be completely fixed. You can close it and when necessary we can open it.

[hartytp]

@gkasprow Sorry, I'd misunderstood you.

If the changes haven't been applied to the designs, we should keep the issue open.

[jbqubit]

• Move power supply status LEDS from bottom side of board to top edge of board (like on Sayma_RTM) so that they're visible from top of crate.

• Include FMC standoffs and screws in BOM.

[jbqubit]

Moved Ethernet discussion to #327.

[jordens]

@gkasprow Is R253 mounted on the three boards we got for Hong Kong or did you remove it because of the RTM configuration conflict?

[gkasprow]

@jordens I'm not 100% sure. I removed all resistors that connect lines CCLK, DIN, DONE, INIT_B, PROGRAM_B to configuration pins of Kintex and connected them to ordinary IO.
R253 did not affect this functionality so probably I left it assembled.

[jordens]

Could you list the differences between the AMCs that we got and the one Florent received? I can't get the second flash to work on any of ours while it worked on Florent's.

[gkasprow]

Florent's board, the one I sent without RTM had Artix FPGA routed to the config pins of Kintex FPGA. I removed R176 ... R180 and installed R200...R204. Are you sure your boards has both SPI FLASH memory chips soldered? I don't remember correctly, but after you discovered that chip select is wrongly connected, I could have decided to not mount second FLASH... It is just about pin 1 of IC23 

[jordens]

Maybe it's not soldered. @sbourdeauducq or @whitequark could you have a look?

What about pin 1 of IC23? The second flash is IC24.

[gkasprow]

I just checked, only a few resistors were changed.

• R257 = DNP - to enable MMC boot without crate
• R208, R205 = DNP. I can't recall why I wanted to make them removed. They should be assembled. R208 is termination resistor for Si5324. R205 is impedance reference for DDR3 controller.
  I found that wanted to remove R223 and R226, but by chance clicked on wrong instance of power schematic of Metlino where these resistors are marked R208 and R205. But this does not explain why FLASH is not working.
• R183 = DNP - to enable PUDC
• R243 = 2k0 - to correct 0.9V value
• R242 = 10k - to make 12V LED brighter

[gkasprow]

@jordens If you publish some bistream with Python library to read/write this FLASH, I can debug it with scope on my board.

[sbourdeauducq]

Yes, both IC23 and IC24 are there on the boards we have.

[gkasprow]

So it seems I have to take care of it. Can you provide me tools to debug it?

[jordens]

@gkasprow Just our branch of openocd and our proxy bitstream, the following script (openocd -f sayma.cfg):

sayma.cfg:

source [find board/sayma_amc.cfg]
# ftdi_location 5:1
# adapter_khz 5000

init
runtest 1000
puts "JTAG scan chain:"
scan_chain
puts "Flash banks:"
flash banks

pld load 0 bscan_spi_xcku040-sayma.bit
reset halt

flash probe xcu.spi
flash probe xcu.spi1
exit

flash read_bank 0 sayma_f0.bin 0 1024
#flash read_bank 1 sayma_f1.bin 0 1024

flash write_image erase sayma_f0.bin 0
#flash write_image erase $bin $addr
flash verify_bank xcu.spi sayma_f0.bin 0
#flash verify_bank $_FLASHNAME $bin $addr

# xcu_program xcu.tap
exit

Gives me

Open On-Chip Debugger 0.10.0-00008-g95aa8855-dirty (2017-09-27-17:23)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 5000 kHz
Info : clock speed 5000 kHz
Info : JTAG tap: xcu.tap tap/device found: 0x13822093 (mfg: 0x049 (Xilinx), part: 0x3822, ver: 0x1)
JTAG scan chain:
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 xcu.tap                Y     0x13822093 0x*3822093     6 0x01  0x03
Flash banks:
#0 : xcu.spi (jtagspi) at 0x00000000, size 0x00000000, buswidth 0, chipwidth 0
#1 : xcu.spi1 (jtagspi) at 0x00000000, size 0x00000000, buswidth 0, chipwidth 0
loaded file bscan_spi_xcku040-sayma.bit to pld device 0 in 3s 935790us
Info : JTAG tap: xcu.tap tap/device found: 0x13822093 (mfg: 0x049 (Xilinx), part: 0x3822, ver: 0x1)
Info : Found flash device 'micron n25q256 3v' (ID 0x0019ba20)
flash 'jtagspi' found at 0x00000000
Error: Unknown flash device (ID 0x00ffffff)

I.e. it only works for the first flash while it used to work for both.

[gkasprow]

@sbourdeauducq the second FLASH is connected to wrong CS pin. AFAIR to be available by JTAG programmer, the CS would need to be routed to G26 pin (FCS2), not K21 (CSO_B). Maybe on previous board you fixed it by removing R253 and bridging with R204 pad.

[jordens]

As mentioned elsewhere, we have a special proxy bitstream that deals with that.
We didn't do any changes on the boards. And Florent only changed the clock/jesd power/jesd termination things.

[gkasprow]

@jordens What about PUDC pin? Maybe your core relies on internal pullups?

[jordens]

We add bitstream pullups on pins R21 and R22 and drive the rest of QSPI1. I don't see how other pullups would affect the second flash.
There is PUDC near SW1:4. Does that mean anything? The schematic has that switch disconnected.
Is the R223/R226 vs R208/R205 mixup something we need to fix? Where are they (remember that we don't have expedition or gerbers/xy)?

[jbqubit]

• Mark J2 on both front and back side of PCB.
• Mark pin 1 of front and back side of J2.

[jordens]

@gkasprow Which boards had the changes you mention in https://github.com/m-labs/sinara/issues/209#issuecomment-332611147 applied? And where are those resistors? Are they here on Florent's board?

That arrangement does not look like what you described in the comment.

[gkasprow]

@jordens well, that looks strange. It seems no config pins are connected here at all.
What board is this? Is it the very first board I shipped to Florent?

[gkasprow]

And are you 100% sure you got it in such state from me? I always use hot air gun but here it looks like somebody was playing with soldering iron :)
Anyway, to gain access to RTM FPGA you need to solder the jumpers R200-R204

[gkasprow]

make sure you remove R176 as well, on the other side of the board, close to FLASH chips

[sbourdeauducq]

Thanks @gkasprow I'll check this on the boards we have today.

[jordens]

That was the photo of florents board I shot 7 months ago. Iirc that had only gone through yours and florents hands.

[gkasprow]

@sbourdeauducq what PUDC level do you want to have on Sayma AMC?
By default pullups were enabled but I noted down that R183 that pulls this line down should be DNP.

[gkasprow]

The same with POR_override.

[sbourdeauducq]

I'm traveling at the moment without access to boards, @hartytp or @jbqubit can you have a look?

[gkasprow]

On RTM you wanted to have pullups enabled.

[hartytp]

@gkasprow I've lost track, are these issues resolved now?

[gkasprow]

mechanical issues are still not resolved.

[hartytp]

@gkasprow where are we with these issues?

[gkasprow]

There are only mechanical and PCB left

[gkasprow]

I'll move it to Sayma_AMC repo

[hartytp]

There are only mechanical and PCB left

Great. Are the AMC/RTM schematics ready to review then apart from the HMC830 active loop filter OpAmp choice?

[hartytp]

I'll move it to Sayma_AMC repo

Thanks. While you're at it, would you mind reviewing all other Sayma related issues in the Sinara repo and closing/moving them as appropriate?