-
Notifications
You must be signed in to change notification settings - Fork 44
API Documentation
The following aims to outline the methods described in the transport layer of casperfpga. These methods are common to all CASPER Hardware, unless otherwise stated.
In [1]: import casperfpga
In [2]: fpga = casperfpga.CasperFpga('hostname')- connect
- disconnect
- read
- blindwrite
- listdev
- deprogram
- set_igmp_version
- upload_to_ram_and_program
- is_connected
- is_running
- _reset_device_info
- test_connection
- read_dram
- write_dram
- write
- read_int
- read_uint
- write_int
- _create_memory_device
- _create_other_device
- device_names_by_container
- devices_by_container
- get_system_information
- estimate_fpga_clock
- check_tx_raw
- get_version_info
connect(timeout=None)
Establish a connection to the KATCP server on the device.
- param timeout: How many seconds to wait after making request. Best practice to use default value.
- return: None
disconnect()
Disconnect from the device server
- return: None
read(device_name, size, offset=0)
Return size (bytes) of binary data with carriage-return and escape_sequence.
- param device_name: Name of memory device from which to read
- param size: How many bytes to read
- param offset: Offset at which to read, in bytes
- return: Binary data string
blindwrite(device_name, data, offset=0)
Unchecked data write, i.e. Write data to device_name and don't wait for it to return.
- param device_name: Name of memory device to write to
- param size: Byte string to be written to device_name
- param offset: Offset at which to write, in bytes
- return: None
listdev()
Get a list of the memory bus items in this design.
- return: List of Memory Devices
deprogram()
Deprogram the FPGA connected by this transport and reset device_information.
- return: None
set-igmp_version(version)
- param version: Updated IGMP Version
- return: None
upload_to_ram_and_program(filename, port=-1, timeout=10, wait_complete=True)
Upload an FPG file to RAM and then program the FPGA.
- param filename: Input file to be uploaded to the FPGA
- param port: The port to use on the rx end, -1 means a random port
- param timeout: How long to wait, in seconds
- param wait_complete: Wait for the transaction to complete
- return: Boolean - True/False - Success/Fail
is_connected()
'Pings' the SKARAB board to see if it is connected and running by attempting to read a register.
- return: Boolean - True/False
is_running()
Is the FPGA programmed and running?
- return: Boolean - True/False
_reset_device_info()
Reset information of devices this FPGA knows about.
- return: None
test_connection()
Write-to and read-from the scratchpad to test the connection to the ROACH/2 Board.
- return: Boolean - Success/Fail
read_dram(size, offset=0)
Reads data from a ROACH's DRAM. Reads are done up to 1MB at a time. The 64MB indirect address register is automatically incremented as necessary.
It returns a string, as per the normal 'read' function. ROACH has a fixed device name for the DRAM.
- param size: Amount of data to be read, in bytes
- param offset: Offset at which to read, in bytes
- return: Binary data string
write_dram(data, offset=0)
Writes data to a ROACH's DRAM. Writes are done up to 512KiB at a time. The 64MB indirect address register is automatically incremented as necessary. ROACH has a fixed device name for the DRAM (dram memory) and so the user does not need to specify the write register.
- param data: Packed binary data string to write
- param offset: Offset at which to write, in bytes
- return: None
write(device_name, data, offset=0)
Write data, then read it to confirm a successful write.
- param device_name: Name of memory device to write data to
- param data: Packed binary data string to write
- param offset: Offset at which to write, in bytes
- return: None
read_int(device_name, word_offset=0)
Read an integer from a memory device. i..e Calls 3. read(device_name, size=4, offset-0) and uses struct library to unpack result into an integer.
- param device_name: Name of memory device to read from
- param word_offset: 32-bit word offset to read from
- return: *Signed 32-bit integer
read_uint(device_name, integer, blindwrite=False, word_offset=0)
Writes an integer to the device specified at the offset specified. Blindwrite is optional.
- param device_name: Name of memory device to read from
- param integer: Integer value to be written
- param blindwrite: True for Blindwrite, default False
- param word_offset: 32-bit word offset to write to
- return: None
write_int(device_name, data, offset=0)
Write data, then read it to confirm a successful write.
- param device_name: Name of memory device to write data to
- param data: Packed binary data string to write
- param offset: Offset at which to write, in bytes
- return: None
_create_memory_device(device_dict, memorymap_dict)
Create memory devices from dictionaries of design information.
- param device_dict: Raw dictionary of information from tagged blocks in Simulink design, keyed on device name
- param memorymap_dict: Dictionary of info that would have been in coreinfo.tab - memory bus info
- return: None
_create_other_devices(device_dict)
Store non-memory device information in a dictionary.
- param device_dict: Raw dictionary of information from tagged blocks in Simulink design, keyed on device name
- return: None
device_names_by_container(container_name)
Return a list of devices in an input container.
- param container_name: Input container to be analysed
- return: List of devices in input container_name
devices_by_container(container)
Get devices using container type.
- param container: Input container to be analysed
- return: Devices associated with input container
get_system_information(filename=None, fpg_info=None)
Get information about the design running on the FPGA. Then populate the dictionary of devices on the bus that can be accessed via listdev.
If filename is given, get it from the input file; otherwise query the host via KATCP.
- param filename: Of input fpg file to be analysed
- param fpg_info: A tuple containing device_info and coreinfo dictionairies
- return: None, the information is populated in the class
estimate_fpga_clock()
Get the estimated clock frequency in MHz of the running FPGA.
- return: Clock Frequency in MHz
check_tx_raw(wait_time=0.2, checks=10)*
Check to see whether this host is transmitting packets without error on all its GbE interfaces.
- param wait_time: In seconds, to wait between checks
- param checks: Number of times to check data
- return: Boolean - True/False - Success/Fail - No errors/Errors
get_version_info()
Get version of casperfpga library.
- return: casperfpga version number