sampleRegMap.json.txt

{	{"name" : "minimal",
		"address" : 0x000002,
		"access"  : "w"
	},
	{"name" : "maximal",
		"address"     : 0x000003,
		"access"      : "r",
		"bit_width"   : 8,
		"lsBit"       : 0,
		"nelms"       : 1,
		"egu"         : "My Units",
		"signed"      : "unsigned",
		"range_top"   : 12,
		"range_bottom": 1,
		"scale_eqn"   : "x",
		"desc"        : "Every field"
		"bits"        :
		{	"wav_ready" : 0x100,
			"bar"       : 0x200
		}
	},
	{"name" : "arc_faults",
		"bits":
		{	"cav1" : 0x0001,
			"cav2" : 0x0002,
			"cav3" : 0x0004,
			"cav4" : 0x0008,
			"cav1Mask" : 0x0100,
			"cav2Mask" : 0x0200,
			"cav3Mask" : 0x0400,
			"cav4Mask" : 0x0800
		},
		"address" : 0xabcdef,
		"access"  : "rw",
		"desc"    : "Arc fault bits and mask for half a cryo module"
	},
	{
	"name" : "shift_reg_signal",
		"address" : 0x000320,
		"access"  : "w",
		"desc"    : "signal FPGA to fill shift register",
	},
	{
	"name" : "shift_reg_first",
		"address" : 0x000321,
		"access"  : "r",
		"desc"    : "data you get on the first read",
	},
	{
	"name" : "shift_reg_second",
		"address" : 0x000321,
		"access"  : "r",
		"desc"    : "data you get on the second read",
	},
	{
	"name" : "shift_reg_third",
		"address" : 0x000321,
		"access"  : "r",
		"desc"    : "data you get on the third read",
	}	
}