EPICS IOC code for LCLS-II superconducting low level RF system, talking to FPGAs using LBNL's protocol
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slaclab/scllrf
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#============================================================== # # Name: README # # Rem: # EPICS IOC Application for LCLS-II superconducting LLRF # # Side: None # # Auth: 28-Jul-2016, (GWBROWN) # Rev: dd-mmm-yyyy, Reviewer's Name (USERNAME) #-------------------------------------------------------------- # Mod: # dd-mmm-yyyy, Reviewer's Name (USERNAME) # coment # #============================================================== # BUILDING: Requires code generated from register maps which are updated in scllrfApp/srcCheetah To generate this code: cd scllrfApp/srcCheetah make make copy Then return to TOP (cd ../..) and make This is the LLRF IOC for LLRF hardware using the network protocol from LBL for register access. This is not part of the LCLS-II "Common Platform". The messages are formatted like: 64 bit nonce 32 bit function/address, 32 bit data ... 32 bit function/address, 32 bit data The message must be smaller than the MTU for UDP, which is 1500 bytes, or about 175 registers. The reply from the FPGA should be: - The nonce echoed back unchanged - For "read" requests, the function/address echoed back then requested 32 bit data - for "write" requests, the function/adderss and data echoed back (There is a bug in some firmware which adds a byte at the end of the response) For simple cases, the code to read and write registers is generated by python Cheetah templates, reading a dictionary/json file of register attributes. LESS SIMPLE CASES: CMOC fixed length waveforms are packed with the data for 8 waveforms interleaved. 32 bit function/address, 32 bit data for waveform 1 32 bit function/address, 32 bit data for waveform 2 ... 32 bit function/address, 32 bit data for waveform 8 32 bit function/address, 32 bit data for waveform 1 32 bit function/address, 32 bit data for waveform 2 ... For PRC, there are up to 8 waveforms interleaved. The selection of waveforms included are in the Trace Keep register. The trace status register bits 24 to 29 are the power of 2 for the array size, e.g. if they contain b000011, then the waveform buffers are 2^3 = 8 registers long, or between one 8 point waveform and 8 1 point waveforms. Interleaving, if more than 1 waveform, is in the same manner as the CMOC waveforms. # End of file
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EPICS IOC code for LCLS-II superconducting low level RF system, talking to FPGAs using LBNL's protocol
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