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Missing NV_NVDLA.verilog and Collecting generated RTL files #208
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Thanks for your swift reply Jzuckerman!
At which step during ESP flow, should I ran the
I wish to try a single-core SoC design with the NVDLA accelerator and below is my expected ESP flow:
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In the third-party accelrator tutorial, authors mentioned that we need the list(.verilog and .sverilog) of hw files. However, they didn't provide .verilog and .sverilog, which make the compiler fail to find the relevant hardware sources files for NVDLA. @jzuckerman Could you please provide an example file(NV_NVDLA.verilog) for us? Or tell us how to list all hardware source files in correct grammar in .verilog. |
The NV_NVDLA.sverilog is empty because there is no System Verilog in the design. The NV_NVDLA.verilog is copied from one of these two files (https://github.com/sld-columbia/esp/tree/dev/accelerators/third-party/NV_NVDLA/config) when you run make NV_NVDLA, depending on whether you are targeting an FPGA or an ASIC. |
Hello there,
I want to use my FPGA-based EDA tool (similar with Zebu from @synopsys) to run a single-core SoC. It utilizes Xilinx Virtex Ultrascale XCVU440 FPGA boards.
My current step is to follow the tutorial on the website: https://www.esp.cs.columbia.edu/docs/singlecore/singlecore-guide/#fpga-prototyping and ran the
make esp-xconfig
command under theesp/socs/xilinx-vcu118-xcvu9p
folder.There are two questions I want to ask:
What should I do here to extract the RTL files for my generated SoC design? A filelist of the SoC design is mandatory for my EDA flow.
At the start of simulation, the terminal reports a message below:
Is anything going wrong with my setup environment?
Thanks for your help!
Best,
Yuchen Cai
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