Skip to content

Commit

Permalink
SoCkit port
Browse files Browse the repository at this point in the history
  • Loading branch information
@somhi
somhi committed Dec 30, 2022
1 parent 10e2b6c commit 83e96dc
Show file tree
Hide file tree
Showing 12 changed files with 711 additions and 350 deletions.
6 changes: 6 additions & 0 deletions Readme.md
View file
@@ -1,3 +1,9 @@
# Template core for [SoCkit (MiSTer) Platform](https://github.com/sockitfpga/MiSTer_SoCkit)

Ported by @somhi from https://github.com/MiSTer-devel/Template_MiSTer

Follows original README.

# Template core for MiSTer

## General description
Expand Down
22 changes: 18 additions & 4 deletions mycore.qsf
View file
Expand Up @@ -13,15 +13,15 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"

set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
Expand Down Expand Up @@ -50,6 +50,16 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name SEED 1

set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ

#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"

#enable it only if 8bit indexed mode is used in core
Expand All @@ -70,4 +80,8 @@ set_global_assignment -name SEED 1
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name VERILOG_FILE sys/I2C_Controller.v
set_global_assignment -name VERILOG_FILE sys/I2C_AV_Config.v

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
2 changes: 0 additions & 2 deletions mycore_Q13.qpf
View file

This file was deleted.

46 changes: 0 additions & 46 deletions mycore_Q13.qsf
View file

This file was deleted.

28 changes: 0 additions & 28 deletions mycore_Q13.srf
View file

This file was deleted.

147 changes: 147 additions & 0 deletions sys/I2C_AV_Config.v
View file
@@ -0,0 +1,147 @@
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.

module I2C_AV_Config ( //Host Side
iCLK,
iRST_N,
// I2C Side
oI2C_SCLK,
oI2C_SDAT
);

// Host Side
input iCLK;
input iRST_N;
// I2C Side
output oI2C_SCLK;
inout oI2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [3:0] LUT_INDEX;
reg [1:0] mSetup_ST;

// Clock Setting
parameter CLK_Freq = 24000000; // 24 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 11;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;



///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N) begin
if(!iRST_N) begin
mI2C_CTRL_CLK <= 1'd0;
mI2C_CLK_DIV <= 16'd0;
end else begin
if (mI2C_CLK_DIV < (CLK_Freq/I2C_Freq))
mI2C_CLK_DIV <= mI2C_CLK_DIV + 16'd1;
else begin
mI2C_CLK_DIV <= 16'd0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end

////////////////////////////////////////////////////////////////////
I2C_Controller u0 (
.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(oI2C_SCLK), // I2C CLOCK
.I2C_SDAT(oI2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N)
);
////////////////////////////////////////////////////////////////////


////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin
if(!iRST_N) begin
LUT_INDEX <= 4'd0;
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end else begin
if(LUT_INDEX < LUT_SIZE) begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1'd1;
mSetup_ST <= 2'd1;
end
1: begin
if(mI2C_END) begin
if(!mI2C_ACK)
mSetup_ST <= 2'd2;
else
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX + 4'd1;
mSetup_ST <= 2'd0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////


///////////////////// Config Data LUT //////////////////////////
always @ (*)
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h009A;//16'h001A; //R0 LINVOL = 1Ah (+4.5bB)
SET_LIN_R : LUT_DATA <= 16'h029A;//16'h021A; //R1 RINVOL = 1Ah (+4.5bB)
SET_HEAD_L : LUT_DATA <= 16'h0479; //R2 LHPVOL = 7Bh (+2dB)
SET_HEAD_R : LUT_DATA <= 16'h0679; //R3 RHPVOL = 7Bh (+2dB)
A_PATH_CTRL : LUT_DATA <= 16'h08D2;//16'h08F8; //R4 DACSEL = 1
D_PATH_CTRL : LUT_DATA <= 16'h0A06; //R5 DEEMP = 11 (48 KHz)
//POWER_ON : LUT_DATA <= 16'h0C00; //R6 all powered ON
POWER_ON : LUT_DATA <= 16'h0C20; //R6 internal oscilator MCLK powered down
//SET_FORMAT : LUT_DATA <= 16'h0E01; //R7 FORMAT=01,16 bit format left justified
SET_FORMAT : LUT_DATA <= 16'h0E02; //R7 FORMAT=10,16 bit format I2S
//SAMPLE_CTRL : LUT_DATA <= 16'h1009; //R8 48KHz,USB-mode
SAMPLE_CTRL : LUT_DATA <= 16'h1008; //R8 48KHz,Normal mode, clkdiv2=0
SET_ACTIVE : LUT_DATA <= 16'h1201; //R9 ACTIVE
default : LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////


endmodule

112 changes: 112 additions & 0 deletions sys/I2C_Controller.v
View file
@@ -0,0 +1,112 @@
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.

module I2C_Controller (
CLOCK,
I2C_SCLK, //I2C CLOCK
I2C_SDAT, //I2C DATA
I2C_DATA, //DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
END, //END transfor
ACK, //ACK
RESET,
//TEST
SD_COUNTER,
SDO
);

input CLOCK;
input [23:0]I2C_DATA;
input GO;
input RESET;
inout I2C_SDAT;
output I2C_SCLK;
output END;
output ACK;
//TEST
output [5:0] SD_COUNTER;
output SDO;

reg SDO;
reg SCLK;
reg END;
reg [23:0]SD;
reg [5:0]SD_COUNTER;

wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK : 1'd0 );
wire I2C_SDAT=SDO ? 1'bz : 1'b0 ;

reg ACK1,ACK2,ACK3;
wire ACK=ACK1 | ACK2 |ACK3;

//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER + 6'd1;
end
end
//----

always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[23];
6'd4 : SDO=SD[22];
6'd5 : SDO=SD[21];
6'd6 : SDO=SD[20];
6'd7 : SDO=SD[19];
6'd8 : SDO=SD[18];
6'd9 : SDO=SD[17];
6'd10 : SDO=SD[16];
6'd11 : SDO=1'b1;//ACK

//SUB ADDR
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[14];
6'd14 : SDO=SD[13];
6'd15 : SDO=SD[12];
6'd16 : SDO=SD[11];
6'd17 : SDO=SD[10];
6'd18 : SDO=SD[9];
6'd19 : SDO=SD[8];
6'd20 : SDO=1'b1;//ACK

//DATA
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[6];
6'd23 : SDO=SD[5];
6'd24 : SDO=SD[4];
6'd25 : SDO=SD[3];
6'd26 : SDO=SD[2];
6'd27 : SDO=SD[1];
6'd28 : SDO=SD[0];
6'd29 : SDO=1'b1;//ACK

//stop
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
6'd31 : SCLK=1'b1;
6'd32 : begin SDO=1'b1; END=1; end

endcase
end
endmodule

0 comments on commit 83e96dc

Please sign in to comment.